MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 76

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MCIMX27LMOP4A

Manufacturer Part Number
MCIMX27LMOP4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX27LMOP4A

Lead Free Status / RoHS Status
Compliant

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Electrical Characteristics
76
1
Note:
SD11 and SD12 are determined by SDRAM controller register settings.
SD1
SD2
SD13
SD14
ID
ADDR
ID
RAS
CAS
SDCLK
WE
SDCLK
CS
SD6
SDRAM clock high-level width
SDRAM clock low-level width
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Data setup time
Data hold time
BA
Table 38. SDR SDRAM Write Timing Parameters (continued)
SD7
Parameter
Table 39. SDRAM Refresh Timing Parameters
Table 38
Figure 39. SDRAM Refresh Timing Diagram
SD11
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
indicates SDRAM requirements. All output signals
NOTE
SD10
Symbol
tCH
tCL
SD1
SD3
Symbol
tDH
tDS
SD2
Min
SD10
3.4
3.4
Min
2.0
1.3
ROW/BA
Freescale Semiconductor
Max
4.1
4.1
Max
Unit
Unit
ns
ns
ns
ns

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