MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 9

• Manufacturer Part Number: MCIMX27LMOP4A
• Manufacturer: Freescale

Specifications of MCIMX27LMOP4A

• Lead Free Status / RoHS Status: Compliant

2.3
This section provides a brief text description of all the modules included in the i.MX27/MX27L devices,
arranged in alphabetical order.
2.3.1
The 1-Wire module provides bi-directional communication between the ARM926 core and the Add-Only
Memory EPROM, DS2502. The 1-Kbit EPROM holds information about the battery and communicates
with the ARM926 Platform using the IP interface. Through the 1-Wire interface, the ARM926 acts as the
bus master while the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence
it is necessary for the ARM926 to poll the 1-Wire to manage the module. The 1-Wire uses an external pin
to connect to the DS2502. Timing requirements are met in hardware with the help of a 1 MHz clock. The
clock divider generates a 1 MHz clock that is used as a time reference by the state machine. Timing
requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide
the necessary signal. The clock must be configured to approximately 1 MHz. You can then set the 1-Wire
register to send and receive bits over the 1-Wire bus.
Freescale Semiconductor
Block Mnemonic
Video Codec
WDOG
WEIM
USB
Module Descriptions
1-Wire Module
Watchdog Timer
Universal Serial
Controllers and
Block Name
(On-The-Go)
Video Codec
Bus–2 Host
Wireless
Interface
External
Module
Module
1 OTG
Table 2. Digital and Analog Modules (continued)
Connectivity
Acceleration
Functional
Peripherals
Grouping
Peripheral
Hardware
Interface
External
Memory
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Timer
The i.MX27/MX27L processors provide two USB Host
controllers and one USBOTG of which:
Video Codec module supports full duplex video codec with 25
fps VGA image resolution, integrates H.264 BP, MPEG-4 SP
and H.263 P3 video processing standard together.
The WDOG module protects against system failures by
providing a method for the system to recover from unexpected
events or programming errors.
The Wireless External Module (WEIM) handles the interface to
devices external to chip, including generation of chip selects,
clock and control for external peripherals and memory. It
provides asynchronous and synchronous access to devices
with SRAM-like interface.
• USB Host 1 is designed to support transceiverless
• USB Host 2 is designed to support transceiverless
• The USBOTG controller offers HS/FS/LS capabilities in Host
connection to the on-board peripherals in Low Speed and
Full Speed mode, and connection to the ULPI
(UTMI+Low-Pin Court) and Legacy Full Speed transceivers
connection to the Cellular Modem Baseband Processor
mode and HS/FS in device mode. In Host mode, the
controller supports direct connection of a FS/LS device
(without external hub). In device (bypass) mode, the OTG
port functions as gateway between the Host 1 Port and the
OTG transceiver.
Brief Description
Functional Description and Application Information
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