E82802AB8 S B48 Intel, E82802AB8 S B48 Datasheet - Page 18
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E82802AB8 S B48
Manufacturer Part Number
E82802AB8 S B48
Description
Manufacturer
Intel
Datasheet
1.E82802AB8_S_B48.pdf
(53 pages)
Specifications of E82802AB8 S B48
Lead Free Status / RoHS Status
Not Compliant
Intel
3.5.
18
®
82802AB/AC Firmware Hub
Operational Effects of Hardware Write-Protect Pins
TBL# and WP#
The TBL# and WP# pins on the Intel FWH provide hardware write protect capabilities. The Top Block
Lock (TBL#) pin, when held low (active), prevents program or block erase operations in the top-most
block of the device where critical code can be stored. When TBL# is high, hardware write protection of
the top block is disabled. The Write Protect (WP#) pin has a function similar to TBL#, but affects all
remaining blocks. WP# operates independently from TBL# and does not affect the lock status of the top
block.
The TBL# and WP# pins must be set to the desired protection state prior to starting a program or erase
operation, since they are sampled at the beginning of the operation. Changing the state of TBL# or WP#
during a program or erase operation may cause unpredictable results.
If the state of TBL# or WP# changes during a program suspend or erase suspend state, the changes to the
device’s locking status do not take place immediately. The suspended operation may be resumed to
successfully complete the program or erase operation. The new lock status will take place after the
program or erase operation completes.
These pins function in combination with the register-based block locking described in Section 4.9. When
active, these pins write-protect the appropriate block(s), regardless of the associated block-locking
registers. (For example, when TBL# is active, writing to the top block is prevented, regardless of the
state of the write-lock bit for the top block’s locking register. In such a case, clearing the write-protect bit
in the register will have no functional effect, even though the register may indicate that the block is no
longer locked. The register may still be set to read-lock the block, if desired.) See Section 4.9 for further
information.
Datasheet
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