RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 60

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
60
Figure 2. PAM Register Attributes
At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable.
As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, the BIOS can be shadowed in system memory to increase the system performance. When
BIOS is shadowed in system memory, it should be copied to the same address location. To shadow
the BIOS, the attributes for that address range should be set to write only. BIOS is shadowed by
first performing a read of that address. This read is forwarded to the expansion bus. The host then
does a write of the same address, which is directed to system memory. After the BIOS is
shadowed, the attributes for that memory area are set to read only so that all writes are forwarded
to the expansion bus. Table 9 and Figure 2 show the PAM registers and the associated attribute
bits:
Reserved
Write Enable (R/W)
1=Enable
0=Disable
Reserved
PAM6
PAM5
PAM4
PAM3
PAM2
PAM1
PAM0
Read Enable (R/W)
1=Enable
0=Disable
R
7
R
6
WE
5
RE
4
3
R
Reserved
R
2
Reserved
WE
Intel
1
Write Enable (R/W)
1=Enable
0=Disable
®
RE
0
82845 MCH for SDR Datasheet
Offset
96h
95h
94h
93h
92h
91h
90h
Read Enable (R/W)
1=Enable
0=Disable
pam
R