RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 78

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.5.37
3.5.38
78
Note: An error can generate one and only one error message via the hub interface. It is software’s
Note: An error can generate one and only one error message via the hub interface. It is software’s
SMICMD—SMI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate a SMI message via the hub interface.
responsibility to make
SERR and SCI error messages are disabled for that same error condition.
SCICMD—SCI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate a SCI message via the hub interface.
responsibility to
and SMI error messages are disabled for that same error condition.
15:2
15:2
Bit
Bit
1
0
1
0
Reserved.
SMI on Multiple-Bit DRAM ECC Error (DMERR).
0 = Disable. For systems not supporting ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SMI message is enabled when the MCH system
SMI on Single-bit ECC Error (DSERR).
0 = Disable. For systems that do not support ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SMI message is enabled when the MCH system
Reserved.
SCI on Multiple-Bit DRAM ECC Error (DMERR).
0 = Disable. For systems not supporting ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SCI message is enabled when the MCH system
SCI on Single-bit ECC Error (DSERR).
0 = Disable. For systems that do not support ECC, this bit must be disabled.
1 = Enable. Generation of the hub interface SCI message is enabled when the MCH system
memory controller detects a multiple-bit error.
memory controller detects a single bit error.
memory controller detects a multiple-bit error.
memory controller detects a single bit error.
make
sure that when an SCI error message is enabled for an error condition, SERR
sure
that when an SMI error message is enabled for an error condition,
CC–CDh
0000h
R/W
16 bits
CE–CDh
0000h
R/W
16 bits
Description
Description
Intel
®
82845 MCH for SDR Datasheet
R