CY7C63743QXC Cypress Semiconductor Corp, CY7C63743QXC Datasheet - Page 24

• Manufacturer Part Number: CY7C63743QXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63743QXC

• Lead Free Status / RoHS Status: Compliant

SPI Interrupt
For SPI, an interrupt request is generated after a byte is received
or transmitted. See Section for details on the SPI interrupt.
SPI Modes for GPIO Pins
The GPIO pins used for SPI outputs (P0.5–P0.7) contain a
bypass mode, as shown in the GPIO block diagram (Figure ).
Whenever the SPI block is inactive (Mode[5:4] = 00), the bypass
value is 1, which enables normal GPIO operation. When SPI
Table 5. SPI Pin Assignments
Document #: 38-08022 Rev. *D
Master Out, Slave In (MOSI)
Master In, Slave Out (MISO)
Slave Select (SS)
CPHA = 0:
CPHA = 1:
SCK (CPOL = 0)
SCK (CPOL = 1)
SS
MOSI/MISO
Data Capture Strobe
Interrupt Issued
MOSI/MISO
Data Capture Strobe
Interrupt Issued
SPI Function
SCK
x
MSB
MSB
GPIO Pin
P0.4
P0.6
P0.7
P0.5
Figure 23. SPI Data Timing
For master mode, firmware sets SS, may use any GPIO pin.
For Slave Mode, SS is an active LOW input.
Data output for master, data input for slave.
Data input for master, data output for slave.
SPI Clock: Output for master, input for slave.
master or slave modes are activated, the appropriate bypass
signals are driven by the hardware for outputs, and are held at 1
for inputs. Note that the corresponding data bits in the Port 0
Data Register must be set to 1 for each pin being used for
an SPI output. In addition, the GPIO modes are not affected by
operation of the SPI block, so each pin must be programmed by
firmware to the desired drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI bypass
value in Figure is always 1, for normal GPIO operation.
Comment
LSB
LSB
CY7C63722C
CY7C63723C
CY7C63743C
x
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