CY7C63743QXC Cypress Semiconductor Corp, CY7C63743QXC Datasheet - Page 40

• Manufacturer Part Number: CY7C63743QXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63743QXC

• Lead Free Status / RoHS Status: Compliant

Register Summary
Document #: 38-08022 Rev. *D
0x13, and
Address
0x0A
0x0B
0x0C
0x0D
0x14,
0x11,
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0xF8
0x10
0x12
0x16
0x15
0x1F
0x20
0x21
0x24
0x25
0x60
0x61
0x40
0x41
0x42
0x43
0x44
0x45
0xFF
Port 0 Data
Port 1 Data
Port 2 Data
GPIO Port 0 Mode 0
GPIO Port 0 Mode 1
GPIO Port 1 Mode 0
GPIO Port 1 Mode 1
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Clock Configuration
USB Device Address
EP0 Mode
EP1, EP2 Mode Register
EP0,1, and 2 Counter
USB Status and Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer LSB
Timer (MSB)
SPI Data
SPI Control
Capture Timer A-Rising,
Data Register
Capture Timer A-Falling,
Data Register
Capture Timer B-Rising,
Data Register
Capture Timer B-Falling,
Data Register
Capture Timer
Configuration
Capture Timer Status
Process Status & Control
Register Name
PS/2 Pull-up
Ext. Clock
First Edge
Received
Wake-up
Resume
Data 0/1
Interrupt
Address
Pending
SETUP
Enable
Enable
Enable
Device
STALL
Toggle
Delay
TCMP
Bit 7
Hold
IRQ
Reserved
Watch Dog
Data Valid
Received
Interrupt
Enable
Enable
VREG
GPIO
Reset
Bit 6
TBF
IN
Wake-up Timer Adjust Bit [2:0]
Reserved
Reserved
Reserved
Prescale Bit [2:0]
Timer B Intr.
Reset-PS/2
D+(SCLK)
Received
Reserved
Interrupt
Interrupt
Capture
Activity
Enable
Mode
Event
State
Bit 5
OUT
USB
Comm Mode [1:0]
Bus
Reserved
Timer A Intr.
D- (SDATA)
Transaction
Transaction
P0[7:0] Interrupt Polarity
P1[7:0] Interrupt Polarity
P0[7:0] Interrupt Enable
P1[7:0] Interrupt Enable
Reserved
LVR/BOR
Capture A Falling Data
Capture B Falling Data
Capture
Capture A Rising Data
Capture B Rising Data
ACKed
ACKed
Enable
Reset
State
Bit 4
P0[7:0] Mode0
P0[7:0] Mode1
P1[7:0] Mode0
P1[7:0] Mode1
Timer Bit [7:0]
Data I/O
P0
P1
Device Address
Low-voltage
Falling Intr
Capture B
Capture B
USB Bus
Interrupt
Suspend
Disable
Activity
Enable
Enable
Falling
Reset
CPOL
Event
Bit 3
SPI
Reserved
Rising Event
Capture B
Rising Intr
Capture B
Precision
1.024 ms
Clocking
Interrupt
Interrupt
Interrupt
Enable
Enable
Enable
Enable
Enable
CPHA
Sense
Bit 2
USB
EP2
Timer Bit [11:8]
Byte Count
Mode Bit
Mode Bit
D+/D- Forcing Bit
P2.1 (Int Clk
Mode Only
Falling Intr
Capture A
Capture A
Reserved
Interrupt
Interrupt
Internal
Disable
Enable
Enable
Enable
Output
Falling
128 μs
Clock
Event
Bit 1
EP1
SCK Select
Rising Event
Reset-PS/2
Activity Intr.
VREG Pin
Capture A
Rising Intr
Capture A
Oscillator
USB Bus
Interrupt
External
Enable
Enable
Enable
Enable
State
Bit 0
EP0
Run
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
WWWWWWWW
Read/Write/
CY7C63722C
CY7C63723C
CY7C63743C
RRRRRRRR
RRRRRRRR
RRRRRRRR
RRRRRRRR
RRRRRRRR
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBB
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBBBBBBB
RBBBBR
B
BB
--
----
----
-----
--
Both/
RR
--
BBBBB
-
RRRR
BBBB
BBBB
BBBB
--
BBB
RR
-
B
Page 40 of 53
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Default/
Section
Reset
See
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