ISP1760BEUM STEricsson, ISP1760BEUM Datasheet - Page 102

• Manufacturer Part Number: ISP1760BEUM
• Manufacturer: STEricsson

Specifications of ISP1760BEUM

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 50. Force Port Enable register (address 0018h) bit
Table 51. Edge Interrupt Count register (address 0340h) bit
Table 52. Edge Interrupt Count register (address 0340h) bit
Table 53. DMA Start Address register (address 0344h) bit
Table 54. DMA Start Address register (address 0344h) bit
Table 55. Power Down Control register (address 0354h) bit
Table 56. Power Down Control register (address 0354h) bit
Table 57. Port 1 Control register (address 0374h) bit
Table 58. Port 1 Control register (address 0374h) bit
Table 59. Interrupt register (address 0310h) bit
Table 60. Interrupt register (address 0310h) bit
Table 61. Interrupt Enable register (address 0314h) bit
Table 62. Interrupt Enable register (address 0314h) bit
Table 63. ISO IRQ Mask OR register (address 0318h) bit
Table 64. INT IRQ Mask OR register (address 031Ch) bit
Table 65. ATL IRQ Mask OR register (address 0320h) bit
Table 66. ISO IRQ Mask AND register (address 0324h) bit
Table 67. INT IRQ Mask AND register (address 0328h) bit
Table 68. ATL IRQ Mask AND register (address 032Ch) bit
Table 69. High-speed bulk IN and OUT: bit allocation . . .59
Table 70. High-speed bulk IN and OUT: bit description . .60
Table 71. High-speed isochronous IN and OUT: bit
Table 72. High-speed isochronous IN and OUT: bit
Table 73. High-speed interrupt IN and OUT: bit
Table 74. High-speed interrupt IN and OUT: bit
Table 75. Microframe description . . . . . . . . . . . . . . . . . .70
Table 76. Start and complete split for bulk: bit allocation .71
Table 77. Start and complete split for bulk: bit
Table 78. SE description . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 79. Start and complete split for isochronous: bit
Table 80. Start and complete split for isochronous: bit
Table 81. Start and complete split for interrupt: bit
CD00222702
Product data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Rev. 08 — 13 April 2010
Table 82. Start and complete split for interrupt: bit
Table 83. Microframe description . . . . . . . . . . . . . . . . . . 82
Table 84. SE description . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 85. Power consumption . . . . . . . . . . . . . . . . . . . . 83
Table 86. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 87. Recommended operating conditions . . . . . . . 84
Table 88. Static characteristics: digital pins . . . . . . . . . . 85
Table 89. Static characteristics: PSW1_N, PSW2_N,
Table 90. Static characteristics: USB interface block (pins
Table 91. Static characteristics: REF5V . . . . . . . . . . . . . 86
Table 92. Dynamic characteristics: system clock timing . 87
Table 93. Dynamic characteristics: CPU interface block 87
Table 94. Dynamic characteristics: high-speed source
Table 95. Dynamic characteristics: full-speed source
Table 96. Dynamic characteristics: low-speed source
Table 97. Register or memory write . . . . . . . . . . . . . . . . 89
Table 98. Register read . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 99. Register access . . . . . . . . . . . . . . . . . . . . . . . 91
Table 100.Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 101.DMA read (single cycle) . . . . . . . . . . . . . . . . . 92
Table 102.DMA write (single cycle) . . . . . . . . . . . . . . . . . 93
Table 103.DMA read (multi-cycle burst) . . . . . . . . . . . . . 94
Table 104.DMA write (multi-cycle burst) . . . . . . . . . . . . . 95
Table 105.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 106.Revision history . . . . . . . . . . . . . . . . . . . . . . . 100
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DM1 to DM3 and DP1 to DP3) . . . . . . . . . . . . 85
electrical characteristics . . . . . . . . . . . . . . . . . 87
electrical characteristics . . . . . . . . . . . . . . . . . 88
electrical characteristics . . . . . . . . . . . . . . . . . 88
Embedded Hi-Speed USB host controller
© ST-ERICSSON 2010. All rights reserved.
ISP1760
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