PDIUSBD12PWTM STEricsson, PDIUSBD12PWTM Datasheet - Page 4

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PDIUSBD12PWTM

Manufacturer Part Number
PDIUSBD12PWTM
Description
Manufacturer
STEricsson
Datasheet

Specifications of PDIUSBD12PWTM

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
TSSOP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PDIUSBD12PWTM
Manufacturer:
ST
Quantity:
4 500
CD00222704
Product data sheet
5.2 Pin description
Table 2.
Symbol
DATA0
DATA1
DATA2
DATA3
GND
DATA4
DATA5
DATA6
DATA7
ALE
CS_N
SUSPEND
CLKOUT
INT_N
RD_N
WR_N
DMREQ
DMACK_N
EOT_N
RESET_N
GL_N
XTAL1
XTAL2
V
D−
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Type
IO2
IO2
IO2
IO2
P
IO2
IO2
IO2
IO2
I
I
I, OD4
O2
OD4
I
I
O4
I
I
I
OD8
I
O
P
A
[1]
Rev. 12 — 8 April 2010
Description
bit 0 of bidirectional data; slew-rate controlled
bit 1 of bidirectional data; slew-rate controlled
bit 2 of bidirectional data; slew-rate controlled
bit 3 of bidirectional data; slew-rate controlled
ground
bit 4 of bidirectional data; slew-rate controlled
bit 5 of bidirectional data; slew-rate controlled
bit 6 of bidirectional data; slew-rate controlled
bit 7 of bidirectional data; slew-rate controlled
Address Latch Enable: The falling edge is used to close the latch of
the address information in a multiplexed address or data bus.
Permanently tied to LOW for separate address or data bus
configuration.
chip select (active LOW)
When the CS_N pin is LOW, ensure that the RESET_N pin is in
inactive state; otherwise, the device will enter test mode.
device is in the suspend state
programmable output clock (slew-rate controlled)
interrupt (active LOW)
read strobe (active LOW)
write strobe (active LOW).
DMA request
DMA acknowledge (active LOW)
end of DMA transfer (active LOW); double up as V
EOT_N is only valid when asserted together with DMACK_N and
either RD_N or WR_N.
reset (active LOW and asynchronous); built-in power-on reset circuit
is present on-chip, so the pin can be tied HIGH to V
When the RESET_N pin is LOW, ensure that the CS_N pin is in
inactive state; otherwise, the device will enter test mode.
GoodLink LED indicator (active LOW)
crystal connection 1 (6 MHz)
crystal connection 2 (6 MHz); if the external clock signal, instead of
the crystal, is connected to XTAL1, then XTAL2 should be floated
voltage supply (4.0 V to 5.5 V)
To operate the IC at 3.3 V, supply 3.3 V to both the V
pins.
USB D− data line
USB peripheral controller with parallel bus
PDIUSBD12
© ST-ERICSSON 2010. All rights reserved.
BUS
CC
CC
sensing.
and VOUT3.3
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