CP82C37A-5 Intersil, CP82C37A-5 Datasheet - Page 9

• Manufacturer Part Number: CP82C37A-5
• Manufacturer: Intersil

Specifications of CP82C37A-5

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Programming
The 82C37A will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.
Note that a problem can occur if a DMA request occurs on
an unmasked channel while the 82C37A is being
programmed. For instance, the CPU may be starting to
reprogram the two byte Address register of channel 1 when
channel 1 receives a DMA request. If the 82C37A is enabled
(bit 2 in the Command register is 0), and channel 1 is
unmasked, a DMA service will occur after only one byte of
the Address register has been reprogrammed. This
condition can be avoided by disabling the controller (setting
bit 2 in the Command register) or masking the channel
before programming any of its registers. Once the
programming is complete, the controller can be
enabled/unmasked.
After power-up it is suggested that all internal locations be
loaded with some known value, even if some channels are
unused. This will aid in debugging.
Register Description
Current Address Register - Each channel has a 16-bit
Current Address register. This register holds the value of the
address used during DMA transfers. The address is
automatically incremented or decremented by one after each
transfer and the values of the address are stored in the
Current Address register during the transfer. This register is
written or read by the microprocessor in successive 8-bit
bytes. See Figure 6 for programming information. It may also
be reinitialized by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP. In memory-to-
memory mode, the channel 0 Current Address register can
be prevented from incrementing or decrementing by setting
the address hold bit in the Command register.
Current Word Count Register - Each channel has a 16-bit
Current Word Count register. This register determines the
number of transfers to be performed. The actual number of
transfers will be one more than the number programmed in
the Current Word Count register (i.e., programming a count
of 100 will result in 101 transfers). The word count is
decremented after each transfer. When the value in the
register goes from zero to FFFFH, a TC will be generated.
This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
9
82C37A
82C37A
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word Count
registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialize these
values are used to restore the current registers to their
original values. The base registers are written
simultaneously with their corresponding current register in 8-
bit bytes in the Program Condition by the microprocessor.
See Figure 6 for programming information. These registers
cannot be read by the microprocessor.
Command Register - This 8-bit register controls the
operation of the 82C37A. It is programmed by the
microprocessor and is cleared by RESET or a Master Clear
instruction. The following diagram lists the function of the
Command register bits. See Figure 4 for Read and Write
addresses.
Command Register
Mode Register - Each channel has a 6-bit Mode register
associated with it. When the register is being written to by
the microprocessor in the Program condition, bits 0 and 1
determine which channel Mode register is to be written.
When the processor reads a Mode register, bits 0 and 1 will
7 6 5 4 3 2 1 0
0
1
0
1
X
0
1
0
1
X
0
1
0
1
X
0
1
0
1
Memory-to-memory disable
Memory-to-memory enable
Channel 0 address hold disable
Channel 0 address hold enable
If bit 0 = 0
Controller enable
Controller disable
Normal timing
Compressed timing
If bit 0 = 1
Fixed priority
Rotating priority
Late write selection
Extended write selection
If bit 3 = 1
DREQ sense active high
DREQ sense active low
DACK sense active low
DACK sense active high
BIT NUMBER
March 20, 2006
FN2967.2