ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 31

• Manufacturer Part Number: ISP1181ADGG
• Manufacturer: STEricsson

Specifications of ISP1181ADGG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 24:
[1]
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DMA Configuration Register: bit allocation
CNTREN
R/W
R/W
R/W
0
0
15
7
0
7
[1]
[1]
12.1.6 Write/Read DMA Configuration
reserved
SHORTP
Table 23:
This command defines the DMA configuration of ISP1181A and enables/disables
DMA transfers. The command accesses the DMA Configuration Register, which
consists of 2 bytes. The bit allocation is given in
DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Configuration
Transaction — write/read 2 bytes
Bit
31 to 24
23 to 10
9
8
7, 6
5
4
3
2
1
0
R/W
R/W
R/W
0
0
14
6
0
6
[1]
[1]
EPDIX[3:0]
Interrupt Enable Register: bit description
Symbol
-
IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.
IEP0IN
IEP0OUT
-
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
IEPSOF
R/W
R/W
R/W
0
0
13
5
0
5
[1]
[1]
Rev. 05 — 08 December 2004
IESOF
Description
reserved; must write logic 0
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
reserved
A logic 1 enables 1 ms interrupts upon detection of Pseudo
SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
R/W
R/W
R/W
0
0
12
4
0
4
[1]
[1]
DMAEN
IEEOT
R/W
R/W
R/W
0
11
3
0
3
0
[1]
reserved
Full-speed USB peripheral controller
Table
reserved
IESUSP
R/W
R/W
R/W
0
10
2
0
2
0
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
24. A bus reset will clear bit
IERESM
ISP1181A
R/W
R/W
R/W
0
0
1
0
9
1
[1]
[1]
BURSTL[1:0]
IERST
R/W
R/W
R/W
0
0
0
0
8
0
30 of 70
[1]
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