ISP1161A1BM,557 NXP Semiconductors, ISP1161A1BM,557 Datasheet - Page 52
ISP1161A1BM,557
Manufacturer Part Number
ISP1161A1BM,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161A1BM557.pdf
(137 pages)
Specifications of ISP1161A1BM,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Philips Semiconductors
Table 18:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
reserved
R/W
R/W
MIE
31
23
15
0
7
0
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 19:
Bit
31
30 to 7
6
RHSC
R/W
R/W
30
22
14
0
6
0
HcInterruptDisable register: bit description
Symbol
MIE
-
RHSC
FNO
R/W
R/W
29
21
13
0
5
0
Rev. 03 — 23 December 2004
Description
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specified in other bits of this register. This
bit is set after a hardware or software reset.
reserved
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
R/W
R/W
UE
28
20
12
0
4
0
reserved
reserved
R/W
R/W
00H
00H
reserved
USB single-chip host and device controller
R/W
R/W
RD
27
19
11
0
3
0
R/W
R/W
SF
26
18
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
reserved
R/W
R/W
25
17
0
9
1
0
R/W
R/W
SO
51 of 136
24
16
0
8
0
0
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