ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 94

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 80.
[1]
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcMode register: bit allocation
13.1.4 DcHardwareConfiguration register (R/W: BBH/BAH)
DMAWD
R/W
0
7
[1]
The DcMode register controls the DMA bus width, resume and suspend modes, interrupt
activity and SoftConnect operation. It can be used to enable debug mode, where all errors
and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode register
Transaction — write/read 1 word
Table 81.
This command is used to access the DcHardwareConfiguration register, which consists of
2 bytes. The first (lower) byte contains the device configuration and control values, the
second (upper) byte holds the clock control bits and the clock division factor. The bit
allocation is given in
values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA operating
mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read DcHardwareConfiguration register
Transaction — write/read 1 word
Bit
7
6
5
4
3
2
1
0
reserved
R/W
6
0
DcMode register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
R/W
5
0
Table
Rev. 04 — 29 January 2009
82. A bus reset will not change any of the programmed bit
Description
A logic 1 selects 16-bit DMA bus width (bus configuration
modes 0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset
value: unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’ mode.
reserved
A logic 1 enables all DC interrupts. Bus reset value: unchanged; for
details, see
A logic 1 enables debug mode where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
reserved
A logic 1 enables SoftConnect (see
if EXTPUL = 1 in the DcHardwareConfiguration register (see
Table
reserved
R/W
4
0
82). Bus reset value: unchanged.
Section
INTENA
USB single-chip host and device controller
R/W
0
3
[1]
8.6.3.
DBGMOD
R/W
0
2
[1]
Section
ISP1161A1
reserved
© ST-NXP Wireless 2009. All rights reserved.
7.5). This bit is ignored
R/W
0
1
[1]
SOFTCT
R/W
93 of 140
0
0
[1]