ATA6823-PHQY Atmel, ATA6823-PHQY Datasheet
ATA6823-PHQY
Specifications of ATA6823-PHQY
Related parts for ATA6823-PHQY
ATA6823-PHQY Summary of contents
Page 1
... QFN32 Package 1. Description The ATA6823 is designed for several body and powertrain applications. The IC is used to drive a continuous current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a PWM signal and a direction signal and allows the use of the motor-control application. The PWM control is performed by the low-side switch ...
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... Figure 1-1. Block Diagram CP CPLO Charge Pump CPIH 12V VG Regulator PBAT Vint 5V Regulator VINT VBAT CP VBATSW VCC 5V Regulator VCC ATA6823 [Preliminary GATE GATE VRES Driver 2 HS Driver 1 OTP 12 bit Logic Control Oscillator VBG Bandgap WD EN1 DIR VMODE /RESET Microcontroller R R GATE ...
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... Receive signal from LIN bus for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R ATA6823 [Preliminary CPLO 22 CPHI VRES 21 ...
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... Related Documents • Qualification of integrated circuits according to Atmel • AEC-Q100-004 and JESD78 (Latch-up) • ESD STM 5.1-1998 • CEI 801-2 (only for information regarding ESD requirements of the PCB) ATA6823 [Preliminary] 4 Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge ...
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... Application 4.1 General Remark This chapter describes the principal application for which the ATA6823 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and envi- ronment, no warranties of fitness for a particular purpose are given. Table 4-1. Component C VINT ...
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... The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in hysteresis ESD-protected by diodes against GND and V this reason the input voltage level must be positive and not higher than V ATA6823 [Preliminary and of undervoltage alarm (V ...
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... EN1 cannot be used to switch from Sleep to Active because CC illustrates the wake-up by LIN. The status PREWAKE is characterized by the acti EN1 was in a valid HIGH state (HIGH for longer than t db ATA6823 [Preliminary] (about V – 2V) the receive part /DATwake VBAT (typically 70 µs) the IC will change to Active will be zero ...
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... Figure 5-1. VBAT ACTIVE SLEEP ATA6823 [Preliminary] 8 Wake-up by pin LIN LIN EN1 RX t < t wake LIN STATUS 55% VBAT 45% VBAT wake LIN VBAT - 1.5V activating "PREWAKE" 4856E–AUTO–07/07 ...
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... T = 12.32 µs, t OSC The times t 4856E–AUTO–07/ order to save current consumption, the watchdog 12.1 ms 9.61 ms and are fixed values with a tolerance of 10%. res d ATA6823 [Preliminary] VBAT t resshort ±1% we get the following typical parameters = 16.88 ms ±10% WD < limited to is OSC ...
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... LIN protocol controller. The transceiver consists of a low side driver (1. mA) with slew rate control, wave shap- ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. ATA6823 [Preliminary] 10 (typically 68 ms for setups in the controller) the watchdog waits for a rising d (close window) and t (open window) form the window watchdog sequence ...
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... This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (V No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC is used for LIN master nodes necessary that the BUS pin be terminated via an external 1 k resistor in series with a diode to VBAT ...
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... X X Note: In order to be able to distinguish between a wake-up from LIN or from EN2, the source of wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1). ATA6823 [Preliminary] 12 Status of the IC Depending on Control Inputs and Detected Failures Driver Stage for External Power MOS DIR ...
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... The time measurement is triggered by the PWM or DIR signal crossing the 50% level. 4856E–AUTO–07/07 12). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible (nF) (tolerance: ±5% ±0.15 µ must be greater than 5 k and should be as close as possible the C CC ATA6823 [Preliminary] plus VG. The charge pump is clocked with a BAT Table 5 ...
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... There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under V > t the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as SC above. ATA6823 [Preliminary] 14 Timing of the Drivers 50 ...
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... Charge pump Charge pump output Switched VBAT Power dissipation Storage temperature Soldering temperature (10s) Notes: 1. For V 13.5V VBAT 2. May be additionally limited by external thermal resistance 4856E–AUTO–07/07 ATA6823 [Preliminary] Pin Name Min GND 0 PGND –0.3 VBAT –0.3 PBAT –0.3 /RESET –0.3 DG1, DG2, DG3 – ...
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... Full functionality 2. H-bridge drivers may be switched off (undervoltage detection) 3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly 4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct 5. H-bridge drivers are switched off ATA6823 [Preliminary] 16 Symbol Value R < ...
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... VBAT ON_VBATSW < 40V VBAT 100 mA load 9V VBAT 100 mA load = 100 mA 29 load regulation DC load = 100 mA 29 load regulation > VBAT ATA6823 [Preliminary] Min Typ Max I 7 VBAT1 I 50 VBAT2 V 4.8 4.94 5.1 INT V 1.225 1.235 1.245 BG V 19.8 22.3 THOV V 1 1.5 ...
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... Tested during characterization only 7. Supplied by charge pump 8. See section “Cross Conduction Time” 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < t ATA6823 [Preliminary] 18 ambient 125°C unless stated otherwise. Pin Symbol 1 ...
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... VAT 8 V _HiSUP_1k_ = 1000 load BUS BAT_max 8 I BUS_PAS_dom = 0V BUS = 12V BAT < 18V BAT 8 I BUS_PAS_rec < 18V BUS V BUS BAT ATA6823 [Preliminary] Min Typ Max 780 t2 T OSC 0.4 OLRES PURES 0.9 BUSrec VBAT 1.2 _LoSUP 2 _HiSUP 0.6 0 ...
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... Tested during characterization only 7. Supplied by charge pump 8. See section “Cross Conduction Time” 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < t ATA6823 [Preliminary] 20 ambient 125°C unless stated otherwise. Pin Symbol = VS ...
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... Pin Symbol = 100 VBAT = 13.5V VBAT = V Sx VBAT = VBAT = 13.5V VBAT = V Sx VBAT = VBAT = ATA6823 [Preliminary] Min Typ Max 100 I 100 VGCPz I 3.3 VGCP V V LxH DSON_LxL DSON_LxH LxL, 100 LxH, –100 PDLx 30 100 DSON_HxL DSON_HxH, ...
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... Tested during characterization only 7. Supplied by charge pump 8. See section “Cross Conduction Time” 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < t ATA6823 [Preliminary] 22 ambient 125°C unless stated otherwise. Pin Symbol = –10 µA ...
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... Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < t 4856E–AUTO–07/07 ambient 125°C unless stated otherwise. Pin Symbol (6) = 0.4V DG (6) = VCC – 0.4V DG ATA6823 [Preliminary] Min Typ Max 0.653 0.667 0.68 V swtcc ...
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... Transients on Power-supply Rail (Battery) The application (including IC and external protection circuitry, see withstand the test pulses in Table 10-1. Test Pulse No Figure 10-1. Pulse 1 (R Figure 10-2. Pulse 2 (R ATA6823 [Preliminary] 24 Table 10-1. Test Pulses Test Duration or Number Level of Pulses –100V 10 min 150V 10 min –200V ...
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... Figure 10-3. Pulse 3a (R Figure 10-4. Pulse 3b (R Figure 10-5. Pulse 4 (R 4856E–AUTO–07/ 12V -200V 100 100 s 200V 12V 0. 12V 5.5V 4.0V 0V < ATA6823 [Preliminary] 100 10% t 90% 90% 10 100 ns t 2000 ms 100 ms 25 ...
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... Static latch-up tested according to AEC-Q100-004 and JESD78. • samples, 0 failures • Electrical post stress testing at room temperature In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the specified current. ATA6823 [Preliminary] 26 Figure 10 and ...
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... Ordering Information Extended Type Number ATA6823-PHQY 13. Package Information Package: QFN Exposed pad 4.7 x 4.7 Dimensions in mm Not indicated tolerances ± 0. Drawing-No.: 6.543-5097.01-4 Issue: 1; 24.02.03 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document ...
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