LH79525N0Q100A0,55 NXP Semiconductors, LH79525N0Q100A0,55 Datasheet
LH79525N0Q100A0,55
Specifications of LH79525N0Q100A0,55
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LH79525N0Q100A0,55 Summary of contents
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Product data sheet FEATURES • Highly Integrated System-on-Chip • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • 32-bit ARM720T™ RISC Core – LH79524: 32-bit External Data Bus – 208 LFBGA package – LH79525: 16-bit External ...
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... LFBGA208 LH79524N0F100A1 LFBGA208 LH79525N0Q100A0 LQFP176 LH79525N0Q100A1 LQFP176 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile fine-pitch ball grid array pack- age; 208 balls plastic low profile fine-pitch ball grid array pack- age; 208 balls plastic low profile quad flat package; 176 leads; ...
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... EXTERNAL MEMORY CONTROLLER USB DEVICE TEST SUPPORT LINEAR REGULATOR ADVANCED HIGH PERFORMANCE BUS (AHB) Figure 1. LH79524/LH79525 block diagram Product data sheet NXP Semiconductors MHz 32.768 kHz OSCILLATOR, PLL(2), POWER MANAGEMENT, and RESET CONTROL CONDITIONED EXTERNAL INTERRUPTS VECTORED INTERRUPT CONTROLLER ETHERNET MAC ...
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... LH79524/LH79525 Figure 2. LH79524 pin configuration (LFBGA208) Figure 3. LH79525 pin configuration (LQFP176) 4 NXP Semiconductors LH79524 ball A1 index area 002aad214 Transparent top view 1 132 LH79525 44 89 002aad213 Rev. 02 — 17 March 2009 System-on-Chip 16 15 Product data sheet ...
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... M16 nCS2/PM2 L14 nCS3/PM3 J15 nBLE0/PM4 J14 nBLE1/PM5 K16 nBLE2/PM6 K15 nBLE3/PM7 Product data sheet NXP Semiconductors Table 2. LH79524 Pin Descriptions O External Address Bus I/O External Data Bus O SDRAM Clock O SDRAM Clock Enable O Data Mask Output to SDRAMs O SDRAM Chip Select ...
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... UARTIRRX1 PB5/SSPTX/I2STXD/ P1 UARTTX1/UARTIRTX1 PB6/INT0/UARTRX0/ N2 UARTIRRX0 6 NXP Semiconductors O Static Memory Output Enable O Static Memory Write Enable I/O USB Data Negative (Differential Pair output, single ended and Differential pair input) I/O USB Data Positive (Differential Pair output, single ended and Differential pair input) ...
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... C7 PG3/LCDVD1 B7 PG4/LCDVD2 Product data sheet NXP Semiconductors General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit- I/O ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1. I/O General Purpose I/O Signal — Port C0; multiplexed with Address A16 I/O General Purpose I/O Signal — ...
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... PN0/D26 A13 PN1/D27 R12 PN2/D24 8 NXP Semiconductors I/O General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3 I/O General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4 I/O General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5 General Purpose I/O Signals — ...
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... VDDA2 Power Analog Power Supply for System PLL J1 VSSA0 Ground F15 VSSA1 Ground E15 VSSA2 Ground Product data sheet NXP Semiconductors I/O General Purpose I/O Signals — Port N3; multiplexed with Data bit D25 I Reset Input O Reset Output I Crystal Input O Crystal Output I 32 ...
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... ETHERTXER C6 PH7 ETHERTX3 C7 PG3 LCDVD1 C8 PG6 LCDVD4 C9 PF3 LCDVD9 C10 PL3 LCDVD13 C11 PN0 D26 C12 PL4 D28 10 NXP Semiconductors Table 3. LH79524 Numerical Pin List (Cont’d) OUTPUT LFBGA FUNCTION NOTES DRIVE NO. AT RESET C13 PE3 C14 PL7 C15 XTALOUT C16 ...
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... PM7 K16 nBLE2 PM6 CTCAP1B/ L1 PA5 CTCMP1B CTCAP1A/ L2 PA4 CTCMP1A CTCAP0A/ L3 PA2 CTCMP0A Product data sheet NXP Semiconductors Table 3. LH79524 Numerical Pin List (Cont’d) OUTPUT LFBGA FUNCTION NOTES DRIVE NO. AT RESET L4 VDD 8 mA L13 8 mA L14 nCS3 8 mA L15 ...
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... R9 A7 R10 A4 R11 A1 R12 PN2 D24 R13 PK6 D22 R14 PK5 D21 R15 PK3 D19 R16 PK0 D16 T1 TDI T2 TEST1 T3 TCK 12 NXP Semiconductors Table 3. LH79524 Numerical Pin List (Cont’d) OUTPUT LFBGA FUNCTION NOTES DRIVE NO. AT RESET T4 PC5 PC2 A15 A12 ...
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... I/O 11 AN0/UL/ AN1/UR/X– AN2/LL/Y+/PJ3 I Product data sheet NXP Semiconductors Table 5. LH79525 Pin Descriptions DESCRIPTION External Address Bus External Data Bus SDRAM Clock SDRAM Clock Enable Data Mask Output to SDRAMs SDRAM Chip Select SDRAM Chip Select Row Address Strobe Column Address Strobe Static Memory Chip Select ...
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... I/O 54 PC5/A21 I/O 14 NXP Semiconductors DESCRIPTION ADC Input 3, 4 wire touch screen Upper Right, 5 wire touch screen Y–; multiplexed with GPIO Port J0 (input only) ADC Input 4, 5 wire touch screen Wiper input; multiplexed with Port J1 (input only) ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5 ADC Input 6 ...
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... PH5/ETHERTX1 I/O 164 PH6/ETHERTX2 I/O Product data sheet NXP Semiconductors DESCRIPTION General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND Flash Write Enable General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND Flash Read Enable General Purpose I/O Signal — ...
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... FUNCTION(S) 1 PI2 ETHERCOL 16 NXP Semiconductors DESCRIPTION General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3 General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management Data Clock General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management Data I/O General Purpose I/O Signals — ...
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... SSPTX/I2STXD/ 39 PB5 UARTTX1/UARTIRTX1 SSPRX/I2SRXD/ 40 PB4 UARTRX1/UARTIRRX1 41 PB3 SSPCLK/I2SCLK 42 PB2 SSPFRM/I2SWS 43 PB1 DREQ/nUARTRTS0 44 PB0 nDACK/nUARTCTS0 45 TDO 46 TDI Product data sheet NXP Semiconductors Table 6. LH79525 Numerical Pin List (Cont’d) OUTPUT PIN FUNCTION NOTES DRIVE NO. AT RESET 47 TEST1 TEST2 49 VSS 50 TMS 51 TCK PC7 53 ...
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... PE1 LCDDCLK 140 VSS 141 PE0 LCDLP/LCDHRLP 142 PF7 LCDFP/LCDSPS 143 PF6 LCDEN/LCDSPL 144 VDD 145 PF5 LCDVD11 18 NXP Semiconductors Table 6. LH79525 Numerical Pin List (Cont’d) OUTPUT PIN FUNCTION NOTES DRIVE NO. AT RESET 146 PF4 147 PF3 148 VSSC ...
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... LCDVD10 MUSTN0 147 LCDVD9 149 LCDVD8 151 LCDVD7 153 LCDVD6 154 LCDVD5 155 LCDVD4 156 LCDVD3 Product data sheet NXP Semiconductors TEST2 nBLE0 Table 8. LH79524 LCD Data Multiplexing STN MONO 8-BIT DUAL SINGLE DUAL PANEL PANEL PANEL MUSTN0 MUSTN0 MUSTN0 ...
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... MMU (Windows CE enabled) The core processor for both is a member of the ARM7T family of processors. For more information, see the ARM document, ‘ARM720T (Rev 3) Technical Reference Manual’, available on ARM’s website at www.ARM.com. 20 NXP Semiconductors DUAL PANEL MUSTN3 MUSTN2 LCD ETHERNET TRANSCEIVER ...
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... INTERNAL SRAM 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 EXTERNAL SDRAM 0x20000000 EXTERNAL SRAM nCS1 0x00000000 REMAP = 00 Figure 5. Memory Remap ‘00’ Product data sheet NXP Semiconductors 0xFFFFFFFF ADVANCED HIGH-PERFORMANCE BUS 0xFFFF1000 0xFFFF0000 0xFFFC0000 0xA0000000 0x80000000 0x60000000 0x40000000 0x20000000 0x00000000 Figure 6. Memory Remap ‘01’ ...
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... Supports single and dual scan color and mono- chrome Super Twisted Nematic (STN) displays with 4- or 8-bit interfaces (LH79524 only) 22 NXP Semiconductors • Supports Thin Film Transistor (TFT) color displays • Programmable resolution up to 1,024 × 1,024 • 15 gray-level mono, 3,375 color STN, and 64 k color TFT support • ...
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... IRQ and FIQ interrupt inputs of the ARM7TDMI processor core. The Interrupt Controller incorporates a hardware Product data sheet NXP Semiconductors interrupt vector logic with programmable priority for interrupt sources. This logic reduces the interrupt response time for IRQ type interrupts compared to solutions using software polling to determine the high- est priority interrupt source ...
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... Stop1 – Stop2 • CPU/Bus clock frequency can be changed on the fly • Selectable clock output • Hardware reset (nRESETIN) and software reset. 24 NXP Semiconductors Table 11. Maximum Clock Speeds NAME Oscillator Clock (CLK OSC) PLL System Clock (CLK PLL) PLL USB Clock 32 ...
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... The interrupt remains active until all compare, capture, and overflow interrupts are cleared. Product data sheet NXP Semiconductors General Purpose Input/Output (GPIO) The LH79524 provides up to 108 bits of programma- ble input/output, and the LH79525 provides 86 bits. ...
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... Communicates with devices in the fast mode as well as the standard mode if both are attached to the bus. 26 NXP Semiconductors SSP To I The SSP to I verts a synchronous serial communication stream in TI DSP-compatible mode into an I nous serial stream ...
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... Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 28. Product data sheet NXP Semiconductors • Front bias-and-control network for touch screen interface and support functions, which are compati- ble with industry-standard 4- and 5-wire touch-sensi- tive panels • ...
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... Current with Linear Regulator disabled IOLR Output Current Range VOLR Output Voltage, Linear Regulator 28 NXP Semiconductors DC/AC Specifications Unless noted, all data provided are based on: • -40°C to +85°C (Industrial temperature range) • VDDC = 1 1.9 V • VDD = 3 3.6 V, VDDA = 1 1.9 V. MIN. TYP. MAX. UNIT 2 ...
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... USB Device (+PLL) 5.6 (+3.3) REFERENCE CLOCK OUTPUT SIGNAL (O) INPUT SIGNAL (I) Product data sheet NXP Semiconductors AC Specifications All signals described in Table 14 relate to transitions RATING UNIT after a reference clock signal. The illustration in Figure 3 represents all cases of these sets of measurement 1.7 to 1.9 V parameters ...
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... Output 50 pF tOHD D[31:0] Input tOVCA nCAS Output 50 pF tOHCA tOVRA nRAS Output 50 pF tOHRA 30 NXP Semiconductors Table 14. AC Signal Characteristics MIN. tWC 3 × tHCLK – 5.0 ns tRC 2 × tHCLK – 5.0 ns tHCLK – 5.5 ns tHCLK – 4.5 ns 14.0 ns 12.5 ns 12.0 ns 0.0 ns ...
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... ETHERTXEN Output 50 pF tOHTXEN tISRXDV ETHERRXDV Input tIHRXDV tISRXD ETHERRX[3:0] Input tIHRXD Product data sheet NXP Semiconductors MIN. MAX. tSDCLK/2 + 4.5 ns tSDCLK/2 – 4.0 ns tSDCLK/2 + 4.5 ns tSDCLK/2 – 4.0 ns tSDCLK/2 + 5.0 ns tSDCLK/2 – 4.0 ns tSDCLK/2 + 4.5 ns tSDCLK/2 – 4.0 ns 19.37 ns SYNCHRONOUS SERIAL PORT (SSP) ...
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... VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down. 32 NXP Semiconductors MIN. TYP. MAX. 10 ...
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... CENTER OF A STEP OF THE ACTUAL 7 TRANSFER CURVE LSB OFFSET ERROR DNL Product data sheet NXP Semiconductors IDEAL TRANSFER CURVE TRANSFER CURVE INTEGRAL NON-LINEARITY CENTER OF STEP 1,015 1,016 1,017 1,018 1,019 Figure 10. ADC Transfer Characteristics Rev. 02 — 17 March 2009 LH79524/LH79525 OFFSET GAIN ...
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... SWAITWRx and SWAITWENx programmed to zero. The write access time is determined by the number of wait states programmed in the SWAITWRx register. 34 NXP Semiconductors In Figure 18, nCSx is asserted coincident (following a small propagation delay) with Valid Address. Data becomes valid another small propagation delay later. Unlike Read transactions, nWE (or nBLEx) assertion is always delayed one HCLK cycle ...
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... Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost. 8. Timing assumes Output Enable Delay register (SWAITOENx) is programmed to 0. Product data sheet NXP Semiconductors tDD_nWAIT_nCS(x) tDD_nWAIT_nOE tA_nWAIT ...
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... HCLK Transaction WST-5 Sequence DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 13. nWAIT Read Sequence (SWAITRDx = 5): nWAIT has no effect on the current transaction 36 NXP Semiconductors tA_nWAIT SQ-3 SQ-2 SQ-1 SQ-0 SQ-4 SQ-3 SQ-2 WST-2 WST-1 nWAIT nWAIT ...
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... Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost. 8. Timing assumes Write Enable Delay register (SWAITWENx) is programmed to 0. Product data sheet NXP Semiconductors tA_nWAIT SQ-2 SQ-1 ...
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... HCLK Transaction WST-5 Sequence DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 16. nWAIT Write Sequence (SWAITWRx = 5): nWAIT has no effect on the current transaction 38 NXP Semiconductors tA_nWAIT SQ-3 SQ-2 SQ-1 SQ-0 SQ-4 SQ-3 SQ-2 nWAIT nWAIT nWAIT WST-2 ...
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... System-on-Chip tASCS HCLK A[23:0] D[31:0] nCS tOEV nOE tBV nBLEx Figure 17. External Static Memory Read, Zero Wait States Product data sheet NXP Semiconductors tRC tDSB tDSCS, tDSOE tAHCS, tAHOE tAHB VALID ADDRESS VALID DATA tCS tOE tDHCS tDHBR tDHOE tBLE DATA CAPTURED Rev. 02 — ...
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... Figure 18. External Static Memory Write, Zero Wait States HCLK A[23:0] D[31:0] nCSx nOE Figure 19. External Static Memory Read with Three Wait States 40 NXP Semiconductors tWC VALID ADDRESS tAW, tAB tCW tCB tDWE tDB tASWE tWP tBP tRC ...
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... System-on-Chip HCLK A[23:0] D[31:0] nCSx nWE or nBLEx Figure 20. External Static Memory Write with Two Wait States Product data sheet NXP Semiconductors tWC VALID ADDRESS VALID DATA Rev. 02 — 17 March 2009 LH79524/LH79525 LH79525-73 41 ...
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... SCLK SDRAMcmd DQMx A[14:0] D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. SDCKE is HIGH. 42 NXP Semiconductors t OVXXX t OHXXX READ NOP NOP NOP t OVDQ t OHDQ t OVA BANK, tISD tIHD ...
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... System-on-Chip Figure 22. SDRAM Bank Activate and Write Product data sheet NXP Semiconductors Rev. 02 — 17 March 2009 LH79524/LH79525 43 ...
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... NOTE: * HCLK is an internal signal provided for reference only. Figure 24. Read, from Peripheral to Memory, Burst Size = 1 44 NXP Semiconductors DACK/DEOT TIMING These timing diagrams indicate when nDACK and DEOT occur in relation to an external bus access to/from the external peripheral that requested the DMA transfer. ...
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... D[31:0] nCSx nWEN nBLE[1:0] nOE DACK0/DEOT0/DEOT1 nDACK1 NOTE: * HCLK is an internal signal, provided for reference only. Figure 26. Read, Peripheral to Memory: Peripheral Burst Size = 4 Product data sheet NXP Semiconductors ADDRESS DATA DATA #1 DATA #2 DATA #3 Rev. 02 — 17 March 2009 LH79524/LH79525 LH79525-7 DATA #4 LH79525-8 ...
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... LH79524/LH79525 Figure 27. Write, Memory-to-Peripheral: Burst Size = 4; Destination Width > External Access Width 46 NXP Semiconductors Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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... System-on-Chip Color LCD Controller Timing Diagrams Product data sheet NXP Semiconductors Figure 28. STN Horizontal Timing Rev. 02 — 17 March 2009 LH79524/LH79525 47 ...
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... LH79524/LH79525 48 NXP Semiconductors Figure 29. STN Vertical Timing Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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... System-on-Chip Product data sheet NXP Semiconductors Figure 30. TFT Horizontal Timing Rev. 02 — 17 March 2009 LH79524/LH79525 49 ...
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... LH79524/LH79525 50 NXP Semiconductors Figure 31. TFT Vertical Timing Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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... PULSE) LCDVD[11:0] (LCD VIDEO DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz. Figure 33. AD-TFT, HR-TFT Vertical Timing Product data sheet NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE 001 002 003 004 005 006 007 008 PIXEL DATA TIMING0:HSW + TIMING0: HBP ...
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... LH79524/LH79525 Synchronous Serial Port The SSP timing is illustrated in Figure 34. Figure 34. Synchronous Serial Port Waveform 52 NXP Semiconductors Rev. 02 — 17 March 2009 System-on-Chip Product data sheet ...
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... The timing for the EMC is presented in the following two illustrations. Figure 35 shows an Ethernet transmit and Figure 36 shows an Ethernet receive. ETHERTXCLK ETHERTXER, ETHERTX[3:0], ETHERTXEN ETHERRXCLK ETHERRXDV, ETHERRX[3:0] Product data sheet NXP Semiconductors tOVTXER, tOVTXD, tOVTXEN tOHTXER, tOHTXD, tOHTXEN Figure 35. Ethernet Transmit Timing tISRXDV, tISRXD tIHRXDV, tIHRXD Figure 36 ...
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... LOW) tRSTOH nRESETOUT hold relative to nRESETIN HIGH VDDCmin VDDC XTAL32 XTAL14 nRESETIN nRESETOUT nRESETIN nRESETOUT 54 NXP Semiconductors Figure 38 shows external reset timing, and Table 18 gives the timing parameters. Table 18. Reset AC Timing DESCRIPTION tOSC32 tRSTIH tOSC14 tRSTOH Figure 37. PLL Start-up tRSTIW tRSTOV Figure 38. External Reset Rev. 02 — ...
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... Tolerance for R1, C1 ≤ 5%. Figure 39. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT) Product data sheet NXP Semiconductors depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. ...
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... R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1 ≤ 5%. Figure 40. Suggested External Components, 10 MHz to 20 MHz Oscillator 56 NXP Semiconductors ENABLE XTALIN MHz R1 1 MΩ C1 ...
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... H D DIMENSIONS (mm are the original dimensions) A UNIT max 0.15 1.45 0.23 mm 1.6 0.25 0.05 1.35 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT1017-1 Figure 41. Package outline SOT1017-1 (LQFP176) Product data sheet NXP Semiconductors ...
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... ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 1.35 0.5 14.1 mm 1.7 0.3 1.20 13.9 0.4 OUTLINE VERSION IEC SOT1019-1 Figure 42. Package outline SOT1019-1 (LFBGA208) 58 NXP Semiconductors ∅ 1/2 e ∅ 1 scale 14.1 0 0.15 0.08 13.9 REFERENCES ...
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... Figure 43. LH79525: LQFP176 PCB Footprint 208-BALL CABGA TOP VIEW A1 BALL PAD CORNER NOTES: 1.00 1. Dimensions in mm. 2. Recommended PCB pad diameter: 0.30 mm. Figure 44. LH79524: LFBGA208 PCB Footprint Product data sheet NXP Semiconductors 21.25 0.4 17 0.80 Rev. 02 — 17 March 2009 LH79524/LH79525 1.70 176LQFP- 208CABGA-FP 59 ...
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... LH79524/LH79525 REVISION HISTORY Document ID Release date Data sheet status LH79524_525_N_2 20090317 Modifications: • Changed document status to “Product data sheet”. LH79524_525_N_1 20070716 60 NXP Semiconductors Table 19. Revision history Change notice Product data sheet - Preliminary data - sheet Rev. 02 — 17 March 2009 System-on-Chip Supersedes ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof ...
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... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...
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... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...
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... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...