DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 28

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Specifications
2-8
Notes:
No.
1.
2.
3.
4.
5.
6.
7.
Characteristics
When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended
when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.
This timing depends on several settings:
• For DPLL disable, using internal oscillator (DPLL Control Register (PCTL) Bit 2 = 0) and oscillator disabled during Stop (PCTL
Bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the
Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,
it is not recommended, and these specifications do not guarantee timings for that case.
• For DPLL disable, using internal oscillator (PCTL Bit 2 = 0) and oscillator enabled during Stop (PCTL Bit 1 = 1), no stabilization
delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).
• For DPLL disable, using external clock (PCTL Bit 2 = 1), no stabilization delay is required and recovery time is defined by the
PCTL Bit 1 and Operating Mode Register Bit 6 settings.
• For DPLL enable, if PCTL Bit 1 is 0, the DPLL is shut down during Stop. Recovering from Stop requires the DPLL to lock. The
DPLL lock procedure duration is defined in Table 2-6 and will be refined after silicon characterization. This procedure is followed
by the stop delay counter. Stop recovery ends when the stop delay counter completes its count.
• The DPLT value for DPLL disable is 0.
Periodically sampled and not 100 percent tested.
For an external clock generator, RESET duration is measured while RESET is asserted, V
active and valid.
For an internal oscillator, RESET duration is measured while RESET is asserted and V
the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other
components connected to the oscillator and reflects worst case conditions.
When the V
device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize
this state to the shortest possible duration.
V
WS = number of wait states (measured in clock cycles, number of T
Use the expression to compute a maximum value.
CCQH
Table 2-7.
= 3.3 V ± 0.3 V, V
CC
A[0–17]
RESET
All Pins
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
Reset, Stop, Mode Select, and Interrupt Timing
CCQL
8
= 1.6 V ± 0.1 V; T
Expression
DSP56321 Technical Data, Rev. 11
Figure 2-3.
J
= –40°C to +100°C, C
Reset Value
Reset Timing
Min
200 MHz
9
Max
C
).
L
Min
= 50 pF.
220 MHz
5
Max
(CONTINUED)
CC
Min
is valid. The specified timing reflects
CC
240 MHz
is valid, and the EXTAL input is
10
First Fetch
Max
Freescale Semiconductor
V
Min
IH
275 MHz
Max
Unit