DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 77

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
M_PCOD
M_PSTP
M_XTLD
M_PEN
;------------------------------------------------------------------------
;
;
;
;------------------------------------------------------------------------
;
M_BCR EQU $FFFFFB
M_DCR EQU $FFFFFA
M_AAR0 EQU $FFFFF9
M_AAR1 EQU $FFFFF8
M_AAR2 EQU $FFFFF7
M_AAR3 EQU $FFFFF6
M_IDR EQU
;
M_BA0W EQU $1F
M_BA1W EQU $3E0
M_BA2W EQU $1C00
M_BA3W EQU $E000
M_BDFW EQU $1F0000
M_BBS EQU 21
M_BLH EQU 22
M_BRH EQU 23
;
M_BCW EQU $3
M_BRW EQU $C
M_BPS EQU $300
M_BPLE EQU 11
M_BME EQU 12
M_BRE EQU 13
M_BSTR EQU 14
M_BRF EQU $7F8000
M_BRP EQU 23
;
M_BAT EQU $3
M_BAAP EQU 2
M_BPEN EQU 3
M_BXEN EQU 4
M_BYEN EQU 5
M_BAM EQU 6
M_BPAC EQU 7
M_BNC EQU $F00
M_BAC EQU $FFF000
;
M_CP EQU $c00000
M_CA EQU 0
M_V EQU 1
EQUATES for BIU
Register Addresses Of BIU
Bus Control Register
DRAM Control Register
Address Attribute Registers
control and status bits in SR
EQU
EQU
EQU
EQU
$FFFFF5
0
1
2
3
DSP56321 Technical Data, Rev. 11
; PLL Clock Output Disable Bit
; STOP Processing State Bit
; XTAL Disable Bit
; PLL Enable Bit
; Bus Control Register
; DRAM Control Register
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; ID Register
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Default Area Wait Control Mask (BDFW0-BDFW4)
; Bus State
; Bus Lock Hold
; Bus Request Hold
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
; Mastership Enable
; Refresh Enable
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh prescaler
; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; Address Muxing
; Packing Enable
; Number of Address Bits to Compare Mask (BNC0-BNC3)
; Address to Compare Bits Mask (BAC0-BAC11)
; mask for CORE-DMA priority bits in SR
; Carry
; Overflow
A-13