PPC405EP-3GB266C Applied Micro Circuits Corporation, PPC405EP-3GB266C Datasheet - Page 30

• Manufacturer Part Number: PPC405EP-3GB266C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405EP-3GB266C

• Family Name: 405EP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.65V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 385
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

PPC405EP – PowerPC 405EP Embedded Processor
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull-
up and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,
and PCI buses should be configured and terminated as follows:
External Bus Control Signals
All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-
impedance state when ExtReset = 0. In addition, as detailed in the PowerPC 405EP Embedded Processor User’s
Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals
between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven
state may affect any devices receiving that particular signal.
The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned.
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Peripheral interface—PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Pull
up PerReady.
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP
to actively drive all of the SDRAM address, data, and control signals.
PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and
actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following:
- Strap the PPC405EP to disable the internal PCI arbiter.
- Individually pull up PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V.
- Pull up PCIReq1:2 through a 3.3kΩ resistor to +3.3V.
- Pull down PCIReq0/Gnt through a 1kΩ resistor to GND.
Revision 1.08 – March 24, 2008
Data Sheet
AMCC