PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet - Page 11

• Manufacturer Part Number: PPC440EPX-SUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-SUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Compliant

Revision 1.30 – February 27, 2009
Internal Buses
The PowerPC 440EPx features six standard internal buses: two Processor Local Buses (PLBs), three On-Chip
Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth
cores such as the PowerPC 440 processor, the DDR SDRAM memory controller, and the PCI bridge connect to
the PLBs. OPB0 hosts lower data rate peripherals. OPB1 is dedicated to USB 2.0 Device support, and OPB2 is
dedicated to USB 2.0 Host. The daisy-chained DCR provides a lower bandwidth path for passing status and
control information between the processor and the other on-chip cores.
Features include:
Security Function (optional)
The built-in security function (PPC440EPx-S only) is a cryptographic engine attached to the 128-bit PLB with built-
in DMA and interrupt controllers.
Features include:
AMCC Proprietary
Data Sheet
• Guarded memory access on 4 KB boundaries
• Data parity checking
• Data transfers occur at PLB bus speeds.
• Power management
• PLB4 (128-bit)
• PLB3 (64-bit)
• OPBs (OPB0, OPB1, and OPB2)
• DCR
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
• Internet Protocol Security (IPSec) features
• Full packet transforms (ESP & AH)
• Complete header and trailer processing (IPv4 and IPv6)
• Multi-mode automatic padding
• "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 166MHz, maximum 5.3GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
– 64-bit implementation of the PLB architecture
– 32-bit address
– 166MHz (1:1 ratio with PLB4), maximum 1.3GB/s (no simultaneous read and write)
– 32-bit data path
– 32-bit address
– 83MHz
– 32-bit data path
– 10-bit address
440EPx – PPC440EPx Embedded Processor
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