PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet - Page 15

• Manufacturer Part Number: PPC440EPX-SUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-SUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Compliant

Revision 1.30 – February 27, 2009
Serial Ports (UART)
Features include:
IIC Bus Controller
Features include:
Serial Peripheral Controller (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Universal Serial Bus 2.0 (USB)
The USB 2.0 interface provides both device and host support. One interface provides host or device support and
operates through an internal PHY. The other interface provides device support only through the UTMI interface
with no internal PHY.
AMCC Proprietary
Data Sheet
• Up to four ports in the following combinations:
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA function on PLB3
• Two IIC interfaces provided
• Support for Philips® Semiconductors I
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Includes an integrated bootstrap controller (BSC) that is multiplexed with the IIC0 interface
• Three-wire serial port interface
• Full-duplex synchronous operation
• SCP bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test
– One 8-pin (UART0)
– Two 4-pin (UART0 and UART1)
– One 4-pin (UART0) and two 2-pin (UART1 and UART2)
– Four 2-pin (UART0, UART1, UART2, and UART3)
2
C Specification, dated 1995
440EPx – PPC440EPx Embedded Processor
15