PPC405EP-3GB200C Applied Micro Circuits Corporation, PPC405EP-3GB200C Datasheet - Page 32

• Manufacturer Part Number: PPC405EP-3GB200C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405EP-3GB200C

• Family Name: 405EP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.65V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 385
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

PPC405EP – PowerPC 405EP Embedded Processor
Table 6. Signal Functional Description (Sheet 2 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
32
Ethernet Interface
PHY0Rx0:1D3:0
EMC0Tx0:1D3:0
PHY0Rx0:1Err
PHY0Rx0:1Clk
PHY0Rx0:1DV
EMC0Tx0:1Err
PHY0Tx0:1Clk
EMC0Tx0:1En
Signal Name
PCIGnt0/Req
EMC0MDClk
PHY0CrS0:1
PHY0Col0:1
EMC0MDIO
PCIReq1:2
PCIGnt1:2
PCIReq input when internal arbiter is used.
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
PCIGnt output when internal arbiter is used.
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHY0RxClk.
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHY0TxClk.
Receive Error. This signal comes from the PHY and is synchronous to
the PHY0RxClk.
Receive Medium clock. This signal is generated by the PHY. If an
EMAC interface is not used, this clock must be present in order to
reset the EMAC.
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
reception.
Carrier Sense signal from the PHY. This is an asynchronous signal.
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
informs the PHY that an error was detected.
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to the
PHY0TxClk.
This clock comes from the PHY and is the Medium Transmit clock. If
an EMAC interface is not used, this clock must be present in order to
reset the EMAC.
Collision signal from the PHY. This is an asynchronous signal.
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with respect to
this clock.
Management Data Input/Output is a bidirectional signal between the
Ethernet controller and the PHY. It is used to transfer control and
status information.
Description
Revision 1.08 – March 24, 2008
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
3.3V PCI
Type
Data Sheet
Notes
1
1
1
1
1
1
1
1
AMCC