PPC440EP-3BC400C Applied Micro Circuits Corporation, PPC440EP-3BC400C Datasheet - Page 81

• Manufacturer Part Number: PPC440EP-3BC400C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3BC400C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 90C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Lead Free Status / RoHS Status: Not Compliant

Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically
close to the PPC440EP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T
system dependent and taken into account by controller initialization software.
Figure 12. DDR SDRAM Read Cycle Timing—Example 1
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Data in Stage 1 D
Data out Stage 1
Data in at RDSP
DQS Stage 1 C
Data out RDSP
with no ECC
Data at pin
DQS at pin
PLB Clock
T
DIN
High
Low
High
Low
T
High
Low
T
D0
SIN
T
D0
T
T
T
P
T
T
SIN
P
DIN
T
D0
= Propagation delay through FFs
= Propagation delay, Stage 1 input to RDSP input w/o ECC
= Delay from DQS at package pin to C on Stage 1 FF.
T
= Delay from data at package pin to D on Stage 1 FF.
D1
D0
P
D1
D0
D1
(1)
D0
D1
D2
D2
D0
D1
D2
D3
D2
D3
D2
D3
D2
D3
Revision 1.29 – May 07, 2008
D2
D3
Data Sheet
T
is
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