MCIMX31LCVMN4D Freescale, MCIMX31LCVMN4D Datasheet - Page 56
MCIMX31LCVMN4D
Manufacturer Part Number
MCIMX31LCVMN4D
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31LCVMN4D.pdf
(108 pages)
Specifications of MCIMX31LCVMN4D
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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1
Display interface clock period average value.
Electrical Characteristics
Table 44
56
Display interface clock period immediate value.
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
IP10
IP11
IP12
IP13
IP14
IP15
IP5
IP6
IP7
IP8
IP9
ID
Tdicp
shows timing parameters of signals presented in
=
⎧
⎪
⎪
⎨
⎪
⎪
⎩
Display interface clock period
Display pixel clock period
Screen width
HSYNC width
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
IP11
T HSP_CLK
Table 44. Synchronous Display Interface Timing Parameters—Pixel Level
T
HSP_CLK
Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse
Parameter
⋅
⎛
⎝
floor
⋅
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
IP13
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Tdicp
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
=
T HSP_CLK
IP14
Symbol
Tdpcp
Tdicp
Thbi1
Thbi2
Tvbi1
Tvbi2
Thsw
Thsd
Tvsw
,
Tsw
⋅
Tsh
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
+
0.5
±
Figure 46
Tdicp
(DISP3_IF_CLK_CNT_D+1) * Tdicp
(SCREEN_WIDTH+1) * Tdpcp
(H_SYNC_WIDTH+1) * Tdpcp
BGXP * Tdpcp
(SCREEN_WIDTH – BGXP – FW) * Tdpcp
H_SYNC_DELAY * Tdpcp
(SCREEN_HEIGHT+1) * Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
BGYP * Tsw
(SCREEN_HEIGHT – BGYP – FH) * Tsw
0.5
⎞
⎠
Start of frame
,
1
IP12
for integer
for fractional
and
Figure
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
Value
HSP_CLK_PERIOD
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
47.
End of frame
Freescale Semiconductor
IP15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns