MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet
MCIMX31L
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MCIMX31L Summary of contents
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... Multimedia Applications Processors 1 Introduction The i.MX31 (MCIMX31) and i.MX31L (MCIMX31L) are multimedia applications processors that represent the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX31 and i.MX31L processors. ...
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Introduction consumption using the most advanced techniques for power saving (DPTC, DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the i.MX31 and i.MX31L provide the optimal performance versus leakage current balance. The performance ...
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... Operating Temp. Device Range ( MCIMX31VKN5 –0°C to +70°C MCIMX31LVKN5 –0°C to +70°C 2 Functional Description and Application Information 2.1 ARM11 Microprocessor Core The CPU of the i.MX31 and i.MX31L is the ARM1136JF-S core based on the ARM v6 architecture. It ® ...
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Functional Description and Application Information The ARM1136JF-S processor core features: • Integer unit with integral EmbeddedICE • Eight-stage pipeline • Branch prediction with return stack • Low-interrupt latency • Instruction and data memory management units (MMUs), managed using micro TLB ...
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Core Core Acronym Name ARM11 or ARM1136 The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM ARM1136 Platform real-time debug modules multi-layer AHB crossbar switch (MAX), and a Vector Floating Processor (VFP). The i.MX31/i.MX31L provide ...
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Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Functional Block Name Mnemonic Grouping FIR Fast InfraRed Connectivity Interface Peripheral GPIO General Pins Purpose I/O Module GPT General Timer Purpose Timer Peripheral GPU Graphics Multimedia Processing ...
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Table 3. Digital and Analog Modules (continued) Block Functional Block Name Mnemonic Grouping SCC Security Security Controller Module SDHC Secured Digital Connectivity Host Controller Peripheral SDMA SDMA System Control Peripheral SIM Subscriber Connectivity Identification Peripheral Module SJC Secure JTAG Debug ...
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Functional Description and Application Information 2.3 Module Descriptions This section provides a brief text description of all the modules included in the i.MX31 and i.MX31L, arranged in alphabetical order. 2.3.1 1-Wire The 1-Wire module provides bi-directional communication between the ARM11 ...
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Digital Audio Mux (AUDMUX) The AUDMUX provides programmable interconnecting for voice, audio, and synchronous data routing between host serial interfaces (i.e. SSI, SAP) and peripheral serial interfaces (i.e. audio and voice codecs). The AUDMUX allows audio system connectivity to ...
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Functional Description and Application Information • Dynamic Process Temperature Compensation (DPTC) reduces active power consumption by adjusting supply voltage accordingly specific process cases, the manner in which the chip was fabricated, and the ambient temperature. • State Retention Voltage (SRV) ...
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External Memory Interface (EMI) The EMI controls all memory accesses external to the i.MX31 and i.MX31L (read/write/erase/program) from all the masters in the system. This is done by using two port interfaces MPG (AHB 32 bit) and MPG64 (AHB ...
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Functional Description and Application Information selects for external devices, with two CS signals covering a range of 128Mbytes, and the other four each covering a range of 32Mbytes.The 128 Mbyte range can be increased to 256Mbytes when combined with combining ...
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Interrupt generation can be programmed for capture, compare, rollover events and the timers offers both restart or free-run modes of operation. 2.3.12 Graphics Processing Unit (GPU) The GPU provides ...
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Functional Description and Application Information The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module eight arrays of fuses (L-Fuses ...
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Keypad Port (KPP) The Keypad Port is designed to interface with keypad matrix with 2-contact or 3-point contact keys. The Keypad Port is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the ...
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Functional Description and Application Information 2.3.19 PCMCIA Host Adapter (PCMCIA) The PCMCIA Host Adapter provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The PCMCIA host adapter module is fully ...
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Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Sampling timer with interrupt • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts • Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal) The ...
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Functional Description and Application Information (specifically platform test access signals). It also serves as a device unique data protection/encryption resource to enable off chip storage of security sensitive data and an internal storage resource which automatically and irrevocably destroys plain ...
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The SDMA memory is constituted of a ROM and a RAM. The ROM contains startup scripts (for example, boot code) and other common utilities which are referenced by the scripts that reside in the RAM. The internal RAM is divided ...
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Functional Description and Application Information includes support for setting breakpoints, Single-Step & Trace and register dump capability. In addition, all memory locations are accessible from the debug port. 2.3.27 Subscriber Identification Module (SIM) The SIM Interface Module (SIM) is designed ...
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SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with ...
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Functional Description and Application Information In addition to the USB cores, the module provides for a Transceiverless Link (TLL) operation on host ports 1 and 2 and allows for routing the OTG transceiver interface to HOST port 1 such that ...
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Watchdog Module (WDOG) The Watchdog (WDOG) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced by software on a periodic ...
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Signal Descriptions Pin Name Group Description GPIO1_1 GPIO1 GPIO reserved for IRQs & DMA events GPIO1_2 GPIO1 GPIO reserved for IRQs & DMA events GPIO1_3 GPIO1 GPIO reserved for IRQs GPIO1_4 GPIO1 GPIO used by USBH1 GPIO1_5 GPIO1 GPIO reserved ...
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Pin Name Group Description BOOT_MODE Clock & Boot Mode 2 2 Reset& PM BOOT_MODE Clock & Boot Mode 3 3 Reset& PM BOOT_MODE Clock & Boot Mode 4 4 Reset& PM CKIL Clock & 32 kHz clk input Reset& PM ...
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Signal Descriptions Pin Name Group Description A13 EMI EIM address 13 A14 EMI EIM address 14 A15 EMI EIM address 15 A16 EMI EIM address 16 A17 EMI EIM address 17 A18 EMI EIM address 18 A19 EMI EIM address ...
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Pin Name Group Description SD23 EMI DDR/SDRAM Data 23 SD24 EMI DDR/SDRAM Data 24 SD25 EMI DDR/SDRAM Data 25 SD26 EMI DDR/SDRAM Data 26 SD27 EMI DDR/SDRAM Data 27 SD28 EMI DDR/SDRAM Data 28 SD29 EMI DDR/SDRAM Data 29 SD30 ...
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Signal Descriptions Pin Name Group Description SDCLK DDR False pad DDR_CLK SDQS0 EMI DDR sample strobe SDQS1 EMI DDR sample strobe SDQS2 EMI DDR sample strobe SDQS3 EMI DDR sample strobe NFWE EMI NANDF NFRE EMI NANDF NFALE EMI NANDF ...
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Pin Name Group Description PC_CD2 EMI PCMCIA PC_WAIT EMI PCMCIA PC_READY EMI PCMCIA PC_PWRON EMI PCMCIA PC_VS1 EMI PCMCIA PC_VS2 EMI PCMCIA PC_BVD1 EMI PCMCIA PC_BVD2 EMI PCMCIA PC_RST EMI PCMCIA IOIS16 EMI PCMCIA PC_RW EMI PCMCIA PC_POE EMI PCMCIA ...
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Signal Descriptions Pin Name Group Description CSI_MCLK IPU (CSI) Sensor Port master Clock ATA_DATA10 CSI_VSYNC IPU (CSI) Sensor port vertical sync CSI_HSYNC IPU (CSI) Sensor port horizontal Sync CSI_PIXCLK IPU (CSI) Sensor port data latch clock I2C_CLK I2C I2C clock ...
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Pin Name Group Description SCK6 AudioPort Tx Serial Clock 6-BT (PP3) SFS6 AudioPort Tx Frame Sync 6-BT (PP3) CSPI1_MOSI CSPI1_ Master Out/Slave In. BB CSPI1_MISO CSPI1_ Slave In/Master Out. BB CSPI1_SS0 CSPI1_ Slave Select (Selectable BB polarity). CSPI1_SS1 CSPI1_ Slave ...
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Signal Descriptions Pin Name Group Description DTR_DCE1 UART1_ CE Bus 11 GPS DSR_DCE1 Full Full UART Bus 4 UART IF RI_DCE1 Full Full UART Bus 5 UART IF DCD_DCE1 Full Full UART IF + ...
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Pin Name Group Description KEY_COL1 Keypad keypad column driver 1 KEY_COL2 Keypad keypad column driver 2 KEY_COL3 Keypad keypad column driver 3 KEY_COL4 Keypad keypad column driver 4 KEY_COL5 Keypad keypad column driver 5 KEY_COL6 Keypad keypad column driver 6 ...
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Signal Descriptions Pin Name Group Description USBOTG_ USBOTG USB OTG FS/ULPI Port DATA1 USBOTG_ USBOTG USB OTG FS/ULPI Port + DATA2 CE Bus USBOTG_ USBOTG USB OTG FS/ULPI Port DATA3 USBOTG_ USBOTG USB OTG FS/ULPI Port DATA4 USBOTG_ USBOTG USB ...
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Pin Name Group Description LD7 IPU – (LCD) LD8 IPU – (LCD) LD9 IPU – (LCD) LD10 IPU – (LCD) LD11 IPU – (LCD) LD12 IPU – (LCD) LD13 IPU – (LCD) LD14 IPU – (LCD) LD15 IPU – (LCD) ...
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Signal Descriptions Pin Name Group Description SD_D_I IPU Data in for Serial Display (LCD) SD_D_IO IPU Data in/out for Serial (LCD) Display SD_D_CLK IPU Serial Display clock (LCD) LCS0 IPU Asynch. Port chip select (LCD) LCS1 IPU Asynch. Port chip ...
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Pin Name Group Description ATA_DIOW ATA – ATA_DMACK ATA – ATA_RESET ATA – CE_ CE – CONTROL CONTROL CLKSS Clock & Clock Source Select at Reset& reset PM CSPI3_MOSI CSPI3_ Master Out/Slave In. MM CSPI3_MISO CSPI3_ Slave In/Master Out. MM ...
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Signal Descriptions Pin Name Group Description NGND5 Noisy – NGND6 Noisy – NGND7 Noisy – NGND8 Noisy – NGND9 Noisy – NGND10 Noisy – NGND21 Noisy – NGND22 Noisy – QVCC Quiet – QVCC1 Quiet – 4 Quiet – 1 ...
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Drive Strength Pin Name Pad Slew Rate Loopback value reset value reset CAPTURE regular sw_pad_ct slow GND GND l_capture[ 0] COMPARE regular sw_pad_ct slow GND GND l_compare [0] WATCHDOG_ regular slow slow GND GND RST PWMO regular sw_pad_ct slow GND ...
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Pin Name Pad Slew Rate Loopback SIMPD0 regular sw_pad_ct slow GND GND sw_pad_ct l_simpd0 l_simpd0 [0] CKIH regular slow slow GND GND RESET_IN regular slow slow GND GND POR regular slow slow GND GND CLKO ddr fast fast GND GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) A12 regular fast fast GND GND sw_pad_ct l_a12[2] A13 regular fast fast GND GND sw_pad_ct l_a13[2] A14 regular fast fast GND GND sw_pad_ct l_a14[2] A15 regular fast fast GND GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) SD9 ddr fast fast GND GND sw_pad_ct l_sd9[2] SD10 ddr fast fast GND GND sw_pad_ct l_sd10[2] SD11 ddr fast fast GND GND sw_pad_ct l_sd11[2] SD12 ddr fast fast GND GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) DQM1 ddr fast fast GND GND sw_pad_ct l_dqm1[2] DQM2 ddr fast fast GND GND sw_pad_ct l_dqm2[2] DQM3 ddr fast fast GND GND sw_pad_ct l_dqm3[2] EB0 regular fast fast GND GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) NFWE regular sw_pad_ct fast GND GND sw_pad_ct l_nfwe_b l_nfwe_b [0] [2] NFRE regular sw_pad_ct fast GND GND sw_pad_ct l_nfre_b[0] l_nfre_b[2] NFALE regular sw_pad_ct fast GND GND sw_pad_ct l_nfale[0] l_nfale[2] NFCLE ...
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Drive Strength Pin Name Pad Slew Rate Loopback D0 regular fast fast GND GND sw_pad_ct l_d0[2] PC_CD1 regular slow slow sw_pad_ct GND l_pc_cd1_ b[9] PC_CD2 regular slow slow GND GND PC_WAIT regular slow slow sw_pad_ct GND l_pc_wait_ b[9] PC_READY regular ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) CSI_D9 regular sw_pad_ct fast GND GND sw_pad_ct l_csi_d9[0] l_csi_d9[2] CSI_D10 regular sw_pad_ct fast GND GND sw_pad_ct l_csi_d10 l_csi_d10 [0] CSI_D11 regular sw_pad_ct fast GND GND sw_pad_ct l_csi_d11 l_csi_d11 [0] CSI_D12 ...
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Drive Strength Pin Name Pad Slew Rate Loopback SCK4 regular sw_pad_ct slow GND GND sw_pad_ct l_sck4[0] l_sck4[2] SFS4 regular sw_pad_ct slow GND GND sw_pad_ct l_sfs4[0] l_sfs4[2] STXD5 regular sw_pad_ct slow GND GND sw_pad_ct l_stxd5[0] l_stxd5[2] SRXD5 regular sw_pad_ct slow GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback CSPI2_SS1 regular sw_pad_ct slow GND GND sw_pad_ct l_cspi2_ss l_cspi2_ss 1[0] CSPI2_SS2 regular sw_pad_ct slow GND GND sw_pad_ct l_cspi2_ss l_cspi2_ss 2[0] CSPI2_SCLK regular sw_pad_ct slow GND GND sw_pad_ct l_cspi2_sc l_cspi2_sc lk[0] CSPI2_SPI_R regular ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) TXD2 regular sw_pad_ct slow GND GND sw_pad_ct l_txd2[0] l_txd2[2] RTS2 regular sw_pad_ct slow GND GND sw_pad_ct l_rts2[0] l_rts2[2] CTS2 regular sw_pad_ct slow GND GND sw_pad_ct l_cts2[0] l_cts2[2] BATT_LINE regular slow ...
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Pin Name Pad Slew Rate Loopback KEY_COL5 regular sw_pad_ct slow GND GND sw_pad_ct l_key_col5 l_key_col5 [0] KEY_COL6 regular sw_pad_ct slow GND GND sw_pad_ct l_key_col6 l_key_col6 [0] KEY_COL7 regular sw_pad_ct slow GND GND sw_pad_ct l_key_col7 l_key_col7 [0] RTCK regular fast fast ...
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Pin Name Pad Slew Rate Loopback USBOTG_DAT regular sw_pad_ct slow GND GND sw_pad_ct A3 l_usbotg_ l_usbotg_ data3[0] data3[2] USBOTG_DAT regular sw_pad_ct slow GND GND sw_pad_ct A4 l_usbotg_ l_usbotg_ data4[0] data4[2] USBOTG_DAT regular sw_pad_ct slow GND GND sw_pad_ct A5 l_usbotg_ l_usbotg_ ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) LD8 regular fast fast GND GND sw_pad_ct l_ld8[2] LD9 regular fast fast GND GND sw_pad_ct l_ld9[2] LD10 regular fast fast GND GND sw_pad_ct l_ld10[2] LD11 regular fast fast GND GND ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) READ regular fast fast GND GND sw_pad_ct l_read[2] VSYNC3 regular fast fast GND GND sw_pad_ct l_vsync3 CONTRAST regular fast fast GND GND sw_pad_ct l_contrast D3_REV regular fast fast GND GND ...
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Pin Name Pad Slew Rate Loopback ATA_RESET regular sw_pad_ct slow GND GND sw_pad_ct l_ata_rese l_ata_rese t_b[0] CE_CONTROL regular fast fast GND GND CLKSS regular fast fast GND GND CSPI3_MOSI regular sw_pad_ct slow GND GND sw_pad_ct l_cspi3_m l_cspi3_m osi[0] CSPI3_MISO regular ...
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Drive Strength Pin Name Pad Slew Rate Loopback Enable (Max) NGND2 – – – – – – NGND3 – – – – – – NGND4 – – – – – – NGND5 – – – – – – NGND6 – ...
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Signal Descriptions 3.1.3 EMI Pins Multiplexing This section discusses the multiplexing of EMI signals. The EMI signals’ multiplexing is done inside the EMI. Table 7 lists the i.MX31 and i.MX31L pin names, pad types, and the memory devices’ equivalent pin ...
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Pin Name Pad Type SD0 ddr SD1 ddr SD2 ddr SD3 ddr SD4 ddr SD5 ddr SD6 ddr SD7 ddr SD8 ddr SD9 ddr SD10 ddr SD11 ddr SD12 ddr SD13 ddr SD14 ddr SD15 ddr SD16 ddr SD17 ddr ...
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Signal Descriptions Pin Name Pad Type DQM1 ddr DQM2 ddr DQM3 ddr EB0 regular EB1 regular OE regular CS0 regular CS1 regular CS2 regular CS3 regular CS4 regular CS5 regular ECB regular LBA regular BCLK regular RW regular RAS regular ...
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Pin Name Pad Type NFRB regular D15 regular D14 regular D13 regular D12 regular D11 regular D10 regular D9 regular D8 regular D7 regular D6 regular D5 regular D4 regular D3 regular D2 regular D1 regular D0 regular PC_CD1 regular ...
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Electrical Characteristics 4 Electrical Characteristics This section provides the chip-level and module-level electrical characteristics for the i.MX31 and i.MX31L: • Section 4.1, “i.MX31 and i.MX31L Chip-Level — Section 4.1.1, “Power • Section 4.2, “Supply Power-Up Requirements and • Section 4.3, ...
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Table 8. i.MX31/i.MX31L Chip-Level Conditions Table 9, “DC Recommended Operating Conditions” Table 10, “Voltage versus Core Frequency” Table 11, “Interface Frequency” Table 12, “DC Absolute Maximum Operating Conditions” Section 4.1.1, “Power Specifications” Table 9 provides the DC recommended operating conditions. ...
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Electrical Characteristics 6 Recommended maximum OVDD operating voltage is 3.1 V for GPIO in either slow or fast mode. Switching duty cycles must be limited to a cumulative duration of 1 year or less (20% duty cycle for a 5yr ...
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Table 12. DC Absolute Maximum Operating Conditions Ref. Num Parameter 1 Supply Voltage 2 Supply Voltage (Level Shift I/O) 3 Input Voltage Range 4 Storage Temperature 5 Absolute Maximum HBM (Human Body Model) ESD stress voltage. 6 Absolute Maximum offset ...
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Electrical Characteristics Table 13. Power Consumption (Typical Values) Mode State Retention • Core VDD (QVCC) = 0.95 V • ARM supply QVCC1 = QVCC = 0.95 V • ARM in well bias • L2 caches are power gated (QVCC4 = ...
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Table 13. Power Consumption (Typical Values) (continued) Mode WAIT (all clocks • All Vdds = 1.2 V (QVCC=QVCC1=QVCC4 = 1.2 V) gated off) • ARM in wait for interrupt mode • MAX is active • L2 cache is stopped but ...
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Electrical Characteristics 3. Powering up of the remainder of noisy and PLL supplies, which can be done simultaneously. The order within the noisy supplies must be maintained, as follows: a) Remainder of noisy supplies (all except for the NVCC2, 21,22, ...
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Table 14. GPIO Pads DC Electrical Parameters Parameter High-level output voltage Low-level output voltage High-level output current, slow slew rate High-level output current, fast slew rate Low-level output current, slow slew rate Low-level output current, fast slew rate 3 High-Level ...
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Electrical Characteristics Table 15. DDR (Double Data Rate) I/O Pads DC Electrical Parameters Parameter 1 High-level output voltage Low-level output voltage 2 High-level output current 2 Low-level output current High-Level DC input voltage of CMOS receiver Low-Level DC input voltage ...
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Output (at pad) Figure 4. Output Pad Transition Time Waveform Table 16. AC Electrical Characteristics of Slow ID Parameter PA1 Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Std Drive) 1 Fast/slow ...
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Electrical Characteristics 4.3.3 Clock Amplifier Module (CAMP) Electrical Characteristics This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. shows clock amplifier electrical characteristics. Table 19. Clock Amplifier Electrical Characteristics Parameter Input Frequency VIL (for square input) VIH (for ...
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Table 21. WR0 Sequence Timing Parameters ID Parameter OW5 Write 0 Low Time OW6 Transmission Time Slot Figure 7 depicts Write 1 Sequence timing, the timing parameters. 1-Wire bus (BATT_LINE) OW7 1-Wire bus (BATT_LINE) OW7 ID Parameter ...
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Electrical Characteristics 4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers) This section discusses ATA electricals and explains how to make sure the ATA interface meets timing. To meet electrical spec on the ATA bus, several requirements must be met. For ...
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Table 23. ATA Timing Parameters (continued) Name tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew2 Max difference in buffer propagation delay for ...
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Electrical Characteristics Table 24. PIO Read Timing Parameters (continued) ATA Parameter Parameter from Figure (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 (min) = (1.5 ...
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Table 25. PIO Write Timing Parameters (continued) ATA Parameter Parameter from Figure 10 – – Avoid bus contention when switching buffer on by making ton long enough. – – Avoid bus contention when switching buffer off by making toff long ...
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Electrical Characteristics Table 26. MDMA Read and Write Timing Parameters (continued) Parameter from ATA Parameter Figure 11, Figure 12 t0 – t0 (min) = (time_d + time_k tg(read) tgr tgr (min-read) = tco + tsu + tbuf + ...
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Figure 14. UDMA In Host Terminates Transfer Timing Diagram Figure 15. UDMA In Device Terminates Transfer Timing Diagram Parameter from ATA Figure 13, Parameter Figure 14, Figure 15 tack tack tack (min) = (time_ack * T) - (tskew1 + tskew2) ...
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Electrical Characteristics Table 27. UDMA In Burst Timing Parameters (continued) Parameter from ATA Figure 13, Parameter Figure 14, Figure 15 tcyc tc1 (tcyc - tskew) > T trp trp trp (min) = time_rp * T - (tskew1 + tskew2 + ...
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Figure 17. UDMA Out Host Terminates Transfer Timing Diagram Figure 18. UDMA Out Device Terminates Transfer Timing Diagram Table 28. UDMA Out Burst Timing Parameters Parameter from ATA Figure 16, Parameter Figure 17, Figure 18 tack tack tack (min) = ...
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Electrical Characteristics Table 28. UDMA Out Burst Timing Parameters (continued) Parameter from ATA Figure 16, Parameter Figure 17, Figure 18 trfs1 trfs trfs = 1 tsui + tco + tbuf + tbuf – tdzfs tdzfs = time_dzfs ...
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CSPIx_DRYN CS11 CSPIx_CS_x CS1 CSPIx_CLK CS7 CS8 CSPIx_DO CS9 CS10 CSPIx_DI Figure 19. CSPI Master Mode Timing Diagram CSPI1_DRYN is connected to CSPI1_CS_1, CSPI2_DRYN is connected to DAM2_T_CLK CSPIx_CS_x CS1 CSPIx_CLK CS9 CS10 CSPIx_DI CS8 CS7 CSPIx_DO ID Parameter CS1 ...
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Electrical Characteristics Table 29. CSPI Interface Timing Parameters (continued) ID Parameter CS9 CSPIx_DI Setup Time CS10 CSPIx_DI Hold Time CS11 CSPIx_DRYN Setup Time 4.3.8 DPLL Electrical Specifications The three PLL’s of the MX31/MX31L (MCU, USB, and Serial PLL) are all ...
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EMI Electrical Specifications This section provides electrical parametrics and timings for EMI module. 4.3.9.1 NAND Flash Controller Interface (NFC) There are two modes of operations for the NFC—default and ONE_CYCLE. Normal NFC mode—using two flash clock cycles for one ...
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Electrical Characteristics NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 22. Address Latch Cycle Timing DIagram NFCLE NFCE NFWE NFALE NFIO[15:0] Figure 23. Write Data Latch Cycle Timing DIagram 84 NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF1 ...
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NFCLE NFCE NFRE NFRB NFIO[15:0] Figure 24. Read Data Latch Cycle Timing DIagram ID Parameter NF1 NFCLE Setup Time NF2 NFCLE Hold Time NF3 NFCE Setup Time NF4 NFCE Hold Time NF5 NF_WP Pulse Width NF6 NFALE Setup Time NF7 ...
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Electrical Characteristics Timing for HCLK is 133 MHz and internal LCLK (flash clock) is 22.5 MHz (45 ns). All timings are listed according to this LCLK frequency (multiples of LCLK phases) except NF16, which is not LCLK related. 4.3.9.1.2 One-Cycle ...
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NFCLE NFCE NFWE NFALE NFIO[15:0] Figure 27. Write Data Latch Cycle Timing DIagram—One Flash Clock Cycle NFCLE NFCE NFRE NFRB NF12_one NFIO[15:0] Figure 28. Read Data Latch Cycle Timing DIagram—One Flash Clock Cycle Table 32. NFC Target Timing Parameters—One Flash ...
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Electrical Characteristics Table 32. NFC Target Timing Parameters—One Flash Clock Cycle (continued) ID NF6_one NF7_one NF8_one NF9_one NF10_one NF11_one NF12_one NF13_one NF14_one NF15_one NF16_one NF17_one High is defined as 80% of signal value and low is defined as 20% of ...
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BCLK (for rising edge timing) BCLK (for falling edge timing) Address CS[ EB[x] LBA Output Data BCLK (for rising edge timing) Input Data DTACK ID WE1 Clock fall to address valid WE2 Clock rise/fall to address invalid ...
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Electrical Characteristics Table 33. WEIM Bus Timing Parameters (continued) ID WE4 Clock rise/fall to CS[x] invalid WE5 Clock rise/fall to RW Valid WE6 Clock rise/fall to RW Invalid WE7 Clock rise/fall to OE Valid WE8 Clock rise/fall to OE Invalid ...
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Test conditions: pad voltage, 1.75 V-1.95 V; pad capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 30, Figure 31, Figure 32, basic WEIM accesses to external memory devices with the timing parameters ...
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Electrical Characteristics BCLK WE1 Last Valid Addr ADDR WE3 CS[x] RW WE11 LBA WE7 OE WE9 EB[y] ECB DATA Figure 32. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— BCLK WE1 ADDR Last Valid Addr WE3 CS[x] WE5 RW ...
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BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE5 RW WE11 LBA OE WE9 EB[y] Figure 34. Muxed A/D Mode Timing Diagram for Asynchronous Write Access— BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] RW LBA OE WE9 ...
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Electrical Characteristics SDCLK SDCLK CS SD4 RAS SD5 CAS SD4 SD5 WE SD6 ADDR ROW/BA DQ DQM Figure 36. SDRAM Read Cycle Timing Diagram Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters ID SD1 SDRAM clock high-level width SD2 SDRAM ...
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Table 34. DDR/SDR SDRAM Read Cycle Timing Parameters (continued SD9 Data out hold time SD10 Active to read/write command period 1 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, ...
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Electrical Characteristics SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 37. SDR SDRAM Write Cycle Timing Diagram Table 35. SDR SDRAM Write Timing Parameters ID SD1 SDRAM clock high-level width SD2 SDRAM clock low-level width ...
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Table 35. SDR SDRAM Write Timing Parameters (continued) ID SD13 Data setup time SD14 Data hold time 1 SD11 and SD12 are determined by SDRAM controller register settings. SDR SDRAM CLK parameters are being measured from the 50% point—that is, ...
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Electrical Characteristics Table 36. SDRAM Refresh Timing Parameters (continued) ID Parameter SD3 SDRAM clock cycle time SD6 Address setup time SD7 Address hold time SD10 Precharge cycle period SD11 Auto precharge command period 1 SD10 and SD11 are determined by ...
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Table 37. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter SD16 CKE output delay time SDCLK SDCLK DQS (output) SD17 DQ (output) DQM (output) SD17 Figure 40. Mobile DDR SDRAM Write Cycle Timing Diagram Table 38. Mobile DDR SDRAM Write Cycle ...
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Electrical Characteristics SDCLK SDCLK SD23 DQS (input) DQ (input) Figure 41. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 39. Mobile DDR SDRAM Read Cycle Timing Parameters ID SD21 DQS - DQ Skew (defines the ...
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Table 40. ETM TRACECLK Timing Parameters ID T Clock period cyc T Low pulse width wl T High pulse width wh T Clock and data rise time r T Clock and data fall time f Figure 43 depicts the setup ...
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Electrical Characteristics 4.3.12 Fusebox Electrical Specifications Table 42. Fusebox Supply Current Parameters Ref. Num 1 1 eFuse Program Current. Current to program one eFuse bit efuse_pgm = 3. eFuse Read Current Current to read an 8-bit eFuse word ...
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Table 44. I2C Module Timing Parameters—I2C Pin I/O Supply=2 Parameter IC1 I2CLK cycle time IC2 Hold time (repeated) START condition IC3 Set-up time for STOP condition IC4 Data hold time IC5 HIGH Period of I2CLK Clock IC6 LOW ...
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Electrical Characteristics Table 45. Supported Camera Sensors (continued) Vendor Fujitsu Micron Matsushita STMicro OmniVision Sharp Motorola National Semiconductor 4.3.14.2 Functional Description There are three timing modes supported by the IPU. 4.3.14.2.1 Pseudo BT.656 Video Mode Smart camera sensors, which include ...
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Start of Frame nth frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK invalid SENSB_DATA[9:0] Figure 45. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes ...
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Electrical Characteristics 4.3.14.3 Electrical Characteristics Figure 47 depicts the sensor interface timing, and SENSB_MCLK (Sensor Input) SENSB_PIX_CLK (Sensor Output) SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC Table 46. Sensor Interface Timing Parameters ID Parameter IP1 Sensor input clock frequency IP2 Data and control setup ...
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Type Display controllers Epson Solomon Systech Hitachi ATI Smart display modules Epson Hitachi Densitron Europe LTD Sharp Sony Digital video encoders Analog Devices (for TV) Crystal (Cirrus Logic) Focus 4.3.15.2 Synchronous Interfaces 4.3.15.2.1 Interface to Active Matrix TFT LCD Panels, ...
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Electrical Characteristics DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_CLK DISPB_D3_DATA Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels 4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics Figure 49 depicts the horizontal timing (timing of one line), ...
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IP13 DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY IP11 Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse Table 48 shows timing parameters of signals presented in Table 48. Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter IP5 Display interface clock period IP6 Display pixel ...
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Electrical Characteristics The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed ...
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Interface to Sharp HR-TFT Panels Figure 52 depicts the Sharp HR-TFT panel interface timing, and CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to Section 4.3.15.2.2, ...
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Electrical Characteristics Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level (continued) ID Parameter IP25 PS rise time IP26 REV toggle time 4.3.15.4 Synchronous Interface to Dual-Port Smart Displays Functionality and electrical characteristics of the synchronous interface to dual-port smart ...
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DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY DISPB_DATA Cb 523 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 261 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 621 622 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 308 309 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Odd Field Figure 53. TV Encoder Interface Timing Diagram Freescale Semiconductor ...
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Electrical Characteristics Interface Encoder, 4.3.15.4.2 The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics” on page 108. 4.3.15.5 Asynchronous ...
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DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock ...
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display ...
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DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not ...
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals ...
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DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA Figure 58. Parallel Interface Timing Diagram—Read Wait States Parallel Interfaces 4.3.15.5.2 Figure 59, Figure 61, Figure 60, and the system 80 and system 68k interfaces. ...
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Electrical Characteristics DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_D#_CS DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) DISPB_DATA (Input) DISPB_DATA (Output) Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram 120 IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 ...
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DISPB_PAR_RS DISPB_D#_CS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) DISPB_DATA (Input) DISPB_DATA (Output) Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram Freescale Semiconductor IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 ...
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Electrical Characteristics DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_D#_CS DISPB_WR (READ/WRITE) DISPB_DATA (Input) DISPB_DATA (Output) Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram 122 IP28, IP27 IP35,IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, ...
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DISPB_PAR_RS DISPB_D#_CS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) DISPB_DATA (Input) DISPB_DATA (Output) Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 51. Asynchronous Parallel Interface Timing Parameters—Access Level ID Parameter IP27 Read system cycle time IP28 Write ...
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Electrical Characteristics Table 51. Asynchronous Parallel Interface Timing Parameters—Access Level (continued) ID Parameter IP36 Controls hold time for write 8 IP37 Slave device data delay 8 IP38 Slave device data hold time IP39 Write data setup time IP40 Write data ...
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. Serial Interfaces 4.3.15.5.3 The IPU supports the following types of asynchronous serial interfaces: • 3-wire (with bidirectional data line) • ...
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Electrical Characteristics 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) Figure 64. 4-wire Serial Interface Timing Diagram Figure 65 depicts timing of the 5-wire serial interface ...
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DISPB_D#_CS DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS DISPB_D#_CS DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS Figure 65. 5-wire Serial Interface (Type 1) Timing Diagram Freescale Semiconductor Write 1 display IF clock cycle RW D7 Preamble Read 1 display IF clock cycle ...
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Electrical Characteristics Figure 66 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries ...
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Serial Interfaces, 4.3.15.5.4 Figure 67 depicts timing of the serial interface. DISPB_SER_RS DISPB_SD_D_CLK DISPB_DATA (Input) DISPB_DATA (Output) Figure 67. Asynchronous Serial Interface Timing Diagram Table 52. Asynchronous Serial Interface Timing Parameters—Access Level ID Parameter IP48 Read system cycle time IP49 ...
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Electrical Characteristics Table 52. Asynchronous Serial Interface Timing Parameters—Access Level (continued) ID Parameter IP56 Controls setup time for write IP57 Controls hold time for write 8 IP58 Slave device data delay 8 IP59 Slave device data hold time IP60 Write ...
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.16 Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 parameters. MSHC_SCLK tSCLKr MSHC_SCLK MSHC_BS MSHC_DATA (Output) ...
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Electrical Characteristics MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Intput) Figure 70. Transfer Operation Timing Diagram (Parallel) The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details ...
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Table 53. Serial Interface Timing Parameters (continued) Signal Parameter MSHC_DATA Output delay time Table 54. Parallel Interface Timing Parameters Signal Parameter H pulse length MSHC_SCLK L pulse length Rise time Fall time Setup time MSHC_BS Hold time Setup time MSHC_DATA ...
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Electrical Characteristics HCLK HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE Figure 71. Write Accesses Timing Diagram—PSHT=1, PSST=1 134 ADDR 1 CONTROL 1 DATA write 1 OKAY ADDR 1 DATA write 1 REG PSST i.MX31/i.MX31L ...
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HCLK HADDR CONTROL RWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE Figure 72. Read Accesses Timing Diagram—PSHT=1, PSST=1 Table 55. PCMCIA Write and Read Timing Parameters Symbol PSHT PCMCIA strobe hold time PSST PCMCIA strobe set up ...
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Electrical Characteristics 4.3.18.1 PWM Timing Figure 73 depicts the timing of the PWM, and System Clock PWM Output ID 1 System CLK frequency 2a Clock high time 2b Clock low time 3a Clock fall time 3b Clock rise time 4a ...
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SDHC Electrical Specifications This section describes the electrical information of the SDHC. 4.3.19.1 SDHC Timing Figure 74 depicts the timings of the SDHC, and MMCx_CLK MMCx_CLK MMCx_CMD MMCx_DAT_0 output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 MMCx_CMD MMCx_DAT_0 input ...
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Electrical Characteristics Table 57. SDHC Interface Timing Parameters (continued) ID Parameter SDHC input / Card Outputs CMD, DAT (Reference to CLK) SD8 Card Output Delay Time during Data Transfer Mode Output Delay time during Identification Mode 1 In low speed ...
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Table 58. SIM Timing Specification—High Drive Strength Num Description 1 SIM Clock Frequency (CLK SIM CLK Rise Time 3 3 SIM CLK Fall Time 4 SIM Input Transition Time (RX, SIMPD) 1 50% duty cycle clock 2 With ...
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Electrical Characteristics 5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received on RX between 400 and 40000 clock cycles after T1. SVEN RST CLK Figure 77. Active-Low-Reset ...
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Spd2rst SIMPD RST CLK DATA_TX SVEN Figure 78. SmartCard Interface Power Down AC Timing Table 59. Timing Requirements for Power Down Sequence Num Description 1 SIM reset to SIM clock stop 2 SIM reset to SIM TX data low 3 ...
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Electrical Characteristics TCK (Input) VIL Data Inputs Data Outputs Data Outputs Data Outputs Figure 80. Boundary Scan (JTAG) Timing Diagram TCK (Input) VIL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 81. Test Access Port Timing Diagram 142 ...
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TCK (Input) TRST (Input) SJ12 ID SJ1 TCK cycle time SJ2 TCK clock pulse width measured at SJ3 TCK rise and fall times SJ4 Boundary scan input data set-up time SJ5 Boundary scan input data hold time SJ6 TCK low ...
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Electrical Characteristics SS2 AD1_TXC (Output) AD1_TXFS (bl) (Output) AD1_TXFS (wl) (Output) AD1_TXD (Output) AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS2 DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in ...
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Table 61. SSI Transmitter with Internal Clock Timing Parameters ID Internal Clock Operation SS1 (Tx/Rx) CK clock period SS2 (Tx/Rx) CK clock high period SS3 (Tx/Rx) CK clock rise time SS4 (Tx/Rx) CK clock low period SS5 (Tx/Rx) CK clock ...
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Electrical Characteristics 4.3.22.2 SSI Receiver Timing with Internal Clock Figure 84 depicts the SSI receiver timing with internal clock, and SS2 AD1_TXC (Output) SS7 AD1_TXFS (bl) (Output) AD1_TXFS (wl) (Output) AD1_RXD (Input) SS48 AD1_RXC (Output) SS2 DAM1_T_CLK (Output) DAM1_T_FS (bl) ...
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Table 62. SSI Receiver with Internal Clock Timing Parameters ID Internal Clock Operation SS1 (Tx/Rx) CK clock period SS2 (Tx/Rx) CK clock high period SS3 (Tx/Rx) CK clock rise time SS4 (Tx/Rx) CK clock low period SS5 (Tx/Rx) CK clock ...
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Electrical Characteristics 4.3.22.3 SSI Transmitter Timing with External Clock Figure 85 depicts the SSI transmitter timing with external clock, and SS23 AD1_TXC (Input) SS27 AD1_TXFS (bl) (Input) AD1_TXFS (wl) (Input) AD1_TXD (Output) AD1_RXD (Input) Note: SRXD Input in Synchronous mode ...
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Table 63. SSI Transmitter with External Clock Timing Parameters ID External Clock Operation SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period SS24 (Tx/Rx) CK clock rise time SS25 (Tx/Rx) CK clock low period SS26 (Tx/Rx) CK clock ...
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Electrical Characteristics 4.3.22.4 SSI Receiver Timing with External Clock Figure 86 depicts the SSI receiver timing with external clock, and SS23 AD1_TXC (Input) SS28 AD1_TXFS (bl) (Input) AD1_TXFS (wl) (Input) AD1_RXD (Input) SS23 DAM1_T_CLK (Input) SS28 DAM1_T_FS (bl) (Input) DAM1_T_FS ...
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Table 64. SSI Receiver with External Clock Timing Parameters (continued) ID SS25 (Tx/Rx) CK clock low period SS26 (Tx/Rx) CK clock fall time SS28 (Rx) CK high to FS (bl) high SS30 (Rx) CK high to FS (bl) low SS32 ...
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Package Information and Pinout Clock T Control out (stp Data out Control in (dir, nxt) Data in Figure 87. USB ULPI Interface Timing Diagram Table 65. USB ULPI Interface Timing Specification Parameter Setup time (control in, 8-bit data ...
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MAPBGA Production Package 457 mm, 0.5 P See Figure 88 for package drawings and dimensions of the production package. Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 Preliminary Package Information and Pinout 153 ...
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Package Information and Pinout 5.1.1 Production Package Outline Drawing Figure 88. Production Package: Mechanical Drawing 154 i.MX31/i.MX31L Advance Information, Rev. 1.4 Preliminary Freescale Semiconductor ...
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MAPBGA Pinout for Production Package Figure 89 shows the i.MX31/i.MX31L ball map of pad locations. Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 Preliminary Package Information and Pinout 155 ...
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A GND GND SFS5 CSPI2 CSPI2_ USBOT USBOT USBOT USB_B _MISO SS2 G_DAT G_DAT G_NXT GND GND STXD4 SRXD CSPI2_ CSPI2_ USBOT USBOT USBOT 5 SS0 SPI_R G_DAT ...
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Figure 66 shows the signal color and signal name legend. Table 67 shows the device pin list, sorted by signal identification, excluding pad locations for ground and power supply voltages. Table 67. i.MX31/i.MX31L BGA (457 Signal ID ...
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Package Information and Pinout Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) 158 Signal ID Pad Location A16 AF15 A17 AF14 A18 AF13 A19 AF12 A2 AB5 A20 AF11 A21 AF10 A22 AF9 ...
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Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) Freescale Semiconductor Signal ID Pad Location CLKSS G26 COMPARE G18 CONTRAST R24 CS0 AE23 CS1 AF23 CS2 AE21 CS3 AD22 CS4 AF24 CS5 AF22 CSI_D10 ...
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Package Information and Pinout Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) 160 Signal ID Pad Location CSPI2_SS1 C6 CSPI2_SS2 A5 CSPI3_MISO G3 CSPI3_MOSI D2 CSPI3_SCLK E1 CSPI3_SPI_RDY G6 CTS1 B11 CTS2 G13 ...
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Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) Freescale Semiconductor Signal ID Pad Location DTR_DCE1 C11 DTR_DCE2 F12 DTR_DTE1 C12 DVFS0 E25 DVFS1 G24 EB0 W21 EB1 Y24 ECB AD23 FGND AB24 FPSHIFT ...
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Package Information and Pinout Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) 162 Signal ID Pad Location KEY_ROW3 A15 KEY_ROW4 G14 KEY_ROW5 B16 KEY_ROW6 F14 KEY_ROW7 A16 LBA AE22 LCS0 P26 LCS1 P21 ...
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Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) Freescale Semiconductor Signal ID Pad Location NFWP U2 NVCC9 J17 OE AB25 PAR_RS R21 PC_BVD1 H2 PC_BVD2 K6 PC_CD1 L7 PC_CD2 K1 PC_POE J7 PC_PWRON ...
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Package Information and Pinout Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) 164 Signal ID Pad Location SD_D_IO P25 SD0 AD18 SD1 AE17 SD1_CLK M7 SD1_CMD L2 SD1_DATA0 M6 SD1_DATA1 L1 SD1_DATA2 L3 ...
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Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) Freescale Semiconductor Signal ID Pad Location SD8 AD15 SD9 AA15 SDBA0 AD7 SDBA1 AE5 SDCKE0 AD21 SDCKE1 AF21 SDCLK AA21 SDCLK AE20 SDQS0 AD16 SDQS1 ...
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Package Information and Pinout Table 67. i.MX31/i.MX31L BGA (457 Signal ID by Pad Grid Location) (continued) 166 Signal ID Pad Location TMS G16 TRSTB B20 TTM_PAD U20 TXD1 F10 TXD2 C13 UVCC V16 USB_BYP A9 USB_OC C10 ...
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Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. 6.1 Revision History Table 68 summarizes revisions to this document since the release ...
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Product Documentation Location Table 23, "ATA Timing Parameters," on page 72 Table 29, "CSPI Interface Timing Parameters," on page 81 Table 33, "WEIM Bus Timing Parameters," on page 89 Table 49, "Synchronous Display Interface Timing Parameters—Access Level," on page 110 ...
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Freescale Semiconductor i.MX31/i.MX31L Advance Information, Rev. 1.4 Preliminary Product Documentation 169 ...
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland ...