NQ80331M667 S L9B8 Intel, NQ80331M667 S L9B8 Datasheet - Page 50

• Manufacturer Part Number: NQ80331M667 S L9B8
• Manufacturer: Intel

Specifications of NQ80331M667 S L9B8

• Lead Free Status / RoHS Status: Not Compliant

Intel
Specification Changes
21.
Issue:
22.
Issue:
Status:
50
®
80331 I/O Processor
‘Issue EMRS3 command’. In order to be JEDEC compliant, these steps should be added to the
memory controller initialization sequence.
Note: Before implementing, check with your DIMM/memory manufacturer to determine if these
steps are necessary. Software should always follow the initialization sequence provided by the
DIMM/memory manufacturer guidelines.
The following pseudo code shows the EMRS initialization steps that are required to be compliant
with the JEDEC DDR-II initialization sequence.
// Step 5 and 6 - EMRS(2) and EMRS(3) programming
if MemoryType is DDR-II
Write 0x2 to DCALADDR (Setting BA[1:0] for EMRS(2))
Write 0x81000003 to DCALCSR (issue EMRS command to CS0)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x81100003 to DCALCSR (issue EMRS command to CS1)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x3 to DCALADDR (Setting BA[1:0] for EMRS(3))
Write 0x81000003 to DCALCSR (issue EMRS command to CS0)
Wait for DCALCSR[31] to report ‘Operation Completed’
Write 0x81100003 to DCALCSR (issue EMRS command to CS1)
Wait for DCALCSR[31] to report ‘Operation Completed’
endif
Case temperature (Tcase) change
To be consistent with the production test environment, the case temperature (Tcase) for the 80331
I/O processor has been changed from 105
Internal Clock Misalignment
Due to non-core
Intel is screening parts to eliminate the probability of occurrence. Until this is fixed in a future
stepping, a screen has been implemented which will screen out parts exhibiting this issue with a
VCC15 greater than 1.46v.
With the screen at 1.46v, the on-board 1.5v power rail should not be allowed to go below 1.46v, as
this would increase the risk of failure. The 1.5v rail minimum is currently specified in the datasheet
as 1.425v, therefore for screened parts, the minimum is changed to 1.46v.
Fixed. This issue was fixed in the D-1 stepping of the product.
Erratum 62, Internal Clock Misalignment Can Cause Processor Hang, on page
ο
c to 95
ο
c.
Specification Update
41,