NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet
NQ80331M667 S L824
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NQ80331M667 S L824 Summary of contents
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... I/O Processor Specification Update April 2006 ® The Intel 80331 I/O Processor may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are doc- umented in this specification update. Order Number: 273930-021US ...
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... Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. ...
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... Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 8 Summary Table of Changes....................................................................... 9 Identification Information.......................................................................... 17 Non-Core Errata....................................................................................... 19 Core Errata .............................................................................................. 43 Specification Changes ............................................................................. 47 Specification Clarifications ....................................................................... 51 Documentation Changes ......................................................................... 61 Specification Update ® Intel 80331 I/O Processor 3 ...
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... Intel 80331 I/O Processor This page intentionally left blank. THIS PAGE INTENTIONALLY LEFT BLANK 4 Specification Update ...
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... Status of Non-Core Errata Specification Update Description Table 1, “Intel ® and Table 2, “Intel 80331 I/O Processor Device ID Registers” and and 30 27 and and 59 19 and 20 15 ® Table 1, “Intel 80331 I/O Processor Die Details” on page Fixed ® 80331 I/O Processor 5 ...
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... Intel 80331 I/O Processor Revision History Date Version Added: • Non-Core Errata January 2005 011 • Specification Clarification • Documentation Change Added: November 2004 010 • Non-Core Errata • Specification Clarification Added: • Specification Clarification • Specification Change 18. September 2004 009 • ...
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... Documentation Changes Updated: • Errata 6, September 2003 001 Initial Release. Specification Update Description 37 through 45. 10 through 13. 9 through 12. 5 through 7. 33 through 36. 3 and 4. 27 through 32. 7 and 8. 6 and 7. 1 and 2. 21 and 26. ® Intel 80331 I/O Processor Revision History 7 ...
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... I/O Processor Design Guide Nomenclature Errata are design defects or errors. These may cause the Intel deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. ...
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... Fixed: No Fix: Row Specification Update ® 80331 I/O Processor. Intel may fix some of the Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Page location of item in this document. ...
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... Intel 80331 I/O Processor Summary Table of Changes Non-Core Errata (Sheet Steppings No. A-1 B-0 C-0 C-1 D Page Status D-1 CAS latency of three not supported for DDR-II On-Die Fix Termination (ODT) Upper PCI signals on Secondary PCI bus are not driven 19 Fixed low during reset ...
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... I C unit hang condition Fix VPD Data Register bit 19 is not read/write ® 29 Fixed Intel XScale Core lockup condition 32-bit region write corrupts ECC immediately after 64-bit 30 Fixed Read-Modify-Write 30 Fixed Reset straps incorrectly sampled on the secondary reset PCI-X to PCI Memory Read double-word near 1MB ...
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... Intel 80331 I/O Processor Summary Table of Changes Non-Core Errata (Sheet Steppings No. A-1 B-0 C-0 C-1 D Page Status D-1 PCI-to-PCI read flow-through with destination TRDY# stalls Fix can cause data corruption 38 Fixed S_PCIXCAP PCI mode threshold is too high Fix No support for burst I/O and configuration read/writes ...
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... Disabling and re-enabling the MMU can hang the core Fix cause it to execute the wrong code Updating the JTAG parallel registers requires an extra TCK Fix rising edge Non-branch instruction in vector table may execute twice after Fix a thumb mode exception ® Intel 80331 I/O Processor Summary Table of Changes Errata 13 ...
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... X 48 Doc self-refresh Intel® 80331 I/O Processor Design Guide change for X 48 Doc Peripheral Bus Interface (PBI) Intel® 80331 I/O Processor Design Guide change for X 49 Doc PCI/-X busses X 49 Doc Internal bus operates at 333 MHz for D-0 stepping ...
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... DMA transactions from local memory to a conventional PCI target Fix can complete out of order Fix SBR1 Programming with Bank 1 Unpopulated 32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit Fix Aligned Writes 60 Fixed Case Temperature Clarification. ® Intel 80331 I/O Processor Summary Table of Changes Specification Clarifications 15 ...
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... Intel 80331 I/O Processor Summary Table of Changes Documentation Changes No. Document Revision Page 1 273942-002 61 2 273942-002 61 3 273942-002 61 4 273942-002 61 5 273942-002 61 6 273942-002 61 7 273942-002 62 8 273942-002 62 9 273942-002 63 10 273823-001 66 11 273943-001 66 12 273942-002 66 13 273942-002 67 14 273942-002 67 15 ...
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... SL824 (Tray), SL828 (T&R) SL8C6 (Tray), SL8CA (T&R) SL825 (Tray), SL829 (T&R) SL8C7 (Tray), SL8CB (T&R) Q604 Q608 Q605 Q609 Q606 Q610 ® Intel 80331 I/O Processor Identification Information Notes 500 Engineering Samples 500 Engineering Samples 500 Engineering Samples 667 Engineering Samples ...
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... Part Number NQ80331M500 D-1 QG80331M500 NQ80331M667 D-1 QG80331M667 NQ80331M800 D-1 QG80331M800 ® Table 2. Intel 80331 I/O Processor Device ID Registers Device and Processor Device ID Stepping (CP15, Register 0 – opcode_2=0) A-1 B-0 C-0 C-1 D-0 D-1 NOTE: Processor core speed can be identified by reading CCLKCFG[3:0] (CP14, register 6) ...
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... For 80331, a new feature was added which keeps internal clocks running on power fail. Status: No Fix. Not to be fixed. See the Specification Update Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “ ...
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... Intel 80331 I/O Processor Non-Core Errata 5. Boundary Scan data gets inverted Problem: Data driven in during boundary scan gets inverted during the capture phase. During parallel loading on a pin, an external zero on data in gets inverted to one for data out. This is a violation of the IEEE 1149 ...
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... Management) at DCh, instead of D4h. D4h is to return zero when read. See the Table , “Summary Table of Changes” on page Specification Update ® Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page 9. ...
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... Intel 80331 I/O Processor Non-Core Errata 14. SDCR0.2 implemented as ‘Reserved’ Problem: The attribute for bit 2 in the MCU SDRAM Control Register 0 (SDCR0) is incorrectly implemented as ‘Reserved’, instead of ‘Read Only’. Since it is ‘reserved’, software cannot rely on reading this bit to determine when DDR or DDR-II memory type is selected. The external state of MEM_TYPE can not be correctly identified by reading this bit ...
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... Status: Fixed. Fixed in C-0 stepping. See the Specification Update Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page ® ...
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... Intel 80331 I/O Processor Non-Core Errata 22. Primary bus pin mode behavior incorrect during reset in the 80331 no bridge mode Problem: In the 80331 no bridge mode (BRG_EN = 0), several unused primary PCI signals provide the wrong behavior during reset. The following signals float (‘Z’ = output disabled) during reset: P_AD[63:0], P_PAR, P_PAR64, P_C/BE[7:0]# ...
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... Note: When neither of these are used by the board vendors during manufacturing testing, there is no issue. Workaround: Intel can provide two BSDL files which allow opens and shorts testing, as long as it does not test the ID and BYPASS instructions. One covers the Intel XScale I/O processor, with the exception that both instruction sets are reduced from since they are operating independently ...
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... Intel 80331 I/O Processor Non-Core Errata 27. SERR# set to incorrect voltage Problem: SERR# is being driven The 80331 might detect SERR# being asserted during boot-up and does not detect SERR# assertion when a device on the PCI-X bus asserts SERR#. Implication: The 80331 falsely detects and logs SERR# assertion during boot-up, due to the SERR# pin being held which the 80331 detects as a logic low (asserted) ...
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... Do not enable preemption control. Keep the default setting of the MCU Preemption Control Register (MPCR, FFFF E540h) bits 3-0 as 0h. Status: Fixed. Fixed in C-0 stepping. See the Specification Update Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page ® ...
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... Intel 80331 I/O Processor Non-Core Errata 2 35 unit hang condition Problem: When a processor reset occurs, the 80331 does not properly detect an idle condition on the I potentially causing the I writing the SDA signal when reset is asserted. The SCL signal goes high, but SDA remains low, signaling that the bus is still busy. Warm reset does not clear up this condition ...
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... The instruction cache line that was being returned from the Flash interface is only partially returned to the Intel XScale • The data cache line from the DDR memory controller is then returned to the Intel XScale core in its entirety. • The Intel XScale line (since the critical instruction was returned first, the core can continue). • ...
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... Intel 80331 I/O Processor Non-Core Errata 38. 32-bit region write corrupts ECC immediately after 64-bit Read-Modify-Write Problem: ECC can be corrupted when the following scenario occurs: • All of memory is initialized to 0s • A 32-bit region is enabled. • Agent A fills the 64-bit memory region with pattern A. ...
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... PCI-X to PCI implementations that do not cross boundary does not experience this issue. Status: Fixed. Fixed in C-0 stepping. See the Specification Update ® Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page 80331 I/O Processor Non-Core Errata 9. ...
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... Intel 80331 I/O Processor Non-Core Errata 42. DMA CRC result is byte reversed Problem: The DMA CRC result value is byte reversed. Example CRC operation with the DMA: CRC Seed: 0x0000 0000 Data Pattern (16 bytes): 0x1234 5678, 0x1457 9098, 0x1234 5678 0x1457 9098 ...
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... Workaround: Use addresses that are DWORD aligned or any byte count other than 4 K. Status: Fixed. Fixed in D-0 stepping. See the Specification Update ® Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page 9 80331 I/O Processor Non-Core Errata 9. ...
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... Intel 80331 I/O Processor Non-Core Errata 47. VCCDDR (VCC25/VCC18) Current Spike Problem: An internal DDR signal gets routed through logic that is powered by the VCC15 rail. This signal gets driven to the wrong level when VCC15 rail is not powered up. This signal controls the input and output enable of all DDR buffers, so when VCC15 is off and VCC25/18 is on, it asserts high and cannot tristate the DDR outputs ...
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... No negative impact expected, since these PCI commands are ‘reserved’ and should not be issued to the ATU. Workaround: No workaround. Status: No Fix. Not to be fixed. See the Specification Update Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page ® 80331 I/O Processor Non-Core Errata 9. ...
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... A software workaround has been identified. The workaround is required for reliable conventional PCI and PCI-X mode operation. The workaround is to write all 1s to the PCI drive strength overrides with the Intel XScale Bit 31 should be set in the following two registers to enable drive strength override: • ...
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... Workaround: Do not enable the core-to-memory port in the BIU Control Register (BIUCR.0). When BIUCR (default condition), the core-to-memory port is disabled and forces all Intel XScale core memory transactions to be issued out the core internal bus (IB) port, therefore avoiding the stall condition. ...
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... Intel 80331 I/O Processor Non-Core Errata 53. PCI-to-PCI read flow-through with destination TRDY# stalls can cause data corruption Problem: PCI-to-PCI read flow-through with destination TRDY# stalls can cause data corruption. Implication: The scenario is a PCI-to-PCI memory read with flow-through enabled (source bus bandwidth is less than or equal to destination bus bandwidth) ...
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... The BIU incorrectly decodes and claims Dual Address Cycle (DAC) addresses in the xxxx_xxxx_FFFF_E000h to xxxx_xxxx_FFFF_FFFFh range (e.g. - ‘x’ represents any bit being set Specification Update Intel Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page ® ...
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... PCI bus after translation. Refer to Section 3.2.2 “Outbound Transactions – Single Address Cycle (SAC) Internal Bus Transactions” in The Intel® 80331 I/O Processor Developer’s Manual (274065) for more information on how the windowing and translation scheme works ...
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... SDRAM. Subsequent warm or cold resets may clear the condition and allow the 80331 to continue operation. Workaround: In most cases, doing a cold or warm reset will clear this condition. Increasing the 1.5v power supply will reduce the probability of a processor hang. Intel is screening parts to eliminate the probability of occurrence (refer to page 50). ...
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... Intel 80331 I/O Processor Non-Core Errata Implication: No negative impact expected. If the routine that reads the IINTVEC/FINTVEC qualifies the return value against IINTSRC0.0/FINTSRC0.0, it will either see there is nothing will validly call the DMA0 End-of-Transfer handler. Workaround: If IINTVEC/FINTVEC equals INTBASE, then re-read the IINTVEC/FINTVEC register. ...
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... For this shared memory region, mark it as write-through memory in the core page table. This prevents the data from ever being written out as dirty. Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update ® Intel 80331 I/O Processor Core Errata ...
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... Intel 80331 I/O Processor Core Errata 3. Performance Monitor Unit event 0x1 can be incremented erroneously by unrelated events Event 0x1 in the performance monitor unit (PMU) can be used to count cycles in which the instruction cache cannot deliver an instruction. The only cycles counted should be those due to an instruction cache miss or an instruction TLB miss ...
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... ID register and the desired register and comparing their values. When the two values are not equal, the desired register exists. ® The Intel XScale core does not implement any CP15 ID code registers other than the Main ID register (opcode2 = 0b000) and the Cache Type register (opcode2 = 0b001). When any of the unimplemented registers are accessed by software (e ...
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... Problem: The IEEE 1149.1 spec states that the effects of updating all parallel JTAG registers should be seen on the falling edge of TCK in the Update-DR state. The Intel XScale incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like hold-reset, JTAG break, and vector traps require either an extra TCK cycle by going to Run-Test-Idle or by cycling through the state machine again in order to trigger the expected hardware behavior ...
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... PCI edge connector. Populate the resistor that connects the net to the correct ball according to the silicon revision. 6. Peripheral Performance Monitor Unit has been de-featured Issue: The Peripheral Performance Monitor Unit has been de-featured. The Intel XScale still functional. Specification Update ® Intel ...
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... Specification Change #9), then DDRRES2 can be pulled down to reduce current draw during self-refresh mode. 15. Intel® 80331 I/O Processor Design Guide change for Peripheral Bus Interface (PBI) Issue: The latest routing guidelines for the Peripheral Bus Interface (PBI) are available upon request and ...
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... DQS being late in the data eye, which could lead to ECC errors. Errors have only been observed when using DIMMs that have a low DQS duty cycle. Note: All of the Intel validation up to this point has been with the default, worst case DLL values and all DIMMs used in validation have passed. ...
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... Due to non-core Erratum 62, Internal Clock Misalignment Can Cause Processor Hang, on page Intel is screening parts to eliminate the probability of occurrence. Until this is fixed in a future stepping, a screen has been implemented which will screen out parts exhibiting this issue with a VCC15 greater than 1.46v. ...
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... Specification Clarifications and 2 GB DDR333 capacities not to be tested in post-silicon validation Issue: Intel is not able to test 64 MB and 2 GB DDR333 DIMMs due to availability. Intel cannot guarantee proper functionality since validation cannot be completed. Status: No Fix. See the Table , “Summary Table of Changes” on page 2 ...
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... Intel 80331 I/O Processor Specification Clarifications 6. Write requirements for the Peripheral Bus Interface Issue: PBI write requirements are: • must set up the Flash or memory to accept writes. • must ensure the write has occurred before another one starts. • illegal to burst writes to the PBI. ...
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... There is a slight lag in the time it takes between clearing a status bit inside the unit and the corresponding bit in the Interrupt Controller Unit Status Register getting cleared. This has the potential of generating a false interrupt, meaning that the Intel XScale handler is not able to find any source reported in the ICU registers. This condition can be avoided by adding a read from any ICU register after the bit is cleared in the local unit before returning from the interrupt handler ...
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... The Core Bus Interface Unit orders transactions based on PCI rules. This allows outgoing writes to pass incoming reads. For most devices on the internal bus, this does not cause problems since the devices function asynchronously with respect to each other. For transactions between the Intel ® ...
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... Peripheral Bus Interface (PBI) bus operate as burst reads (in other words, two 16-bit read cycles). All the read transactions from the Intel XScale PBI devices (in other words, SRAM, Flash, etc.) are translated to burst reads with burst size of 2, even though there is no necessity to generate a burst transaction ...
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... Clockouts, arbitration and interrupt inputs are not provided on the primary PCI bus. When the ATU generates configuration cycles they are not forwarded from the secondary PCI bus to the primary PCI bus. Also, the Intel XScale When using the 80331 in embedded designs, keep the bridge enabled (BRG_EN=1) and connect the primary PCI bus as follows: 1 ...
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... Modify the loop such that the write is not done on every iteration. Status: No Fix. See the Table , “Summary Table of Changes” on page 25. Interleaving descriptors with D-0 AAU Issue: The P+Q capability is enabled in the AAU globally (ACR.3), not on a descriptor by descriptor basis. Specification Update ® Intel 80331 I/O Processor Specification Clarifications ...
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... Therefore, when using DDR-I memory, the RCVDLY default setting of 5 may need to be changed operate correctly with a specific DIMM based on the board layout. For example, the Redboot reference code provided by Intel uses a value allow for a wider compatibility with various DIMMs. Status: No Fix. See the Table , “ ...
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... ODT (On Die Termination) signals (ODT[1:0]) which are used with DDR-II DIMMs to turn on termination during writes. Section 8.7.6 in the Intel® 80331 I/O Processor Developer’s Manual (273942) states, “If bank 1 is unpopulated, SBR1[6:0] is programmed either with all zeroes or a value equal to SBR0[6:0].” To clarify this statement for single-banked DDR-II DIMMs, if bank 1 is unpopulated, then the entire SBR1 must be programmed the same as SBR0 ...
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... Issue: Internal models indicate that certain elevated case temperatures (Tcase) of the 80331 may cause elevated field failures in later years of operation. This clarification is precautionary, as Intel has not seen any failures of the 80331 products in the field. Internal modeling data indicates that the degree of failure risk decreases with lower operating frequency (i.e. – ...
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... Problem: Incorrect and incomplete information regarding the Core Performance Monitoring Unit. Workaround: Changes include additional control registers (Interrupt, Overflow, Event) and two more counter (PMN2 and PMN3). See the Intel XScale manual as ‘XSC2’ core. ® Affected Docs: Intel 80331 I/O Processor Developer’s Manual 4 ...
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... Recovery wait states 010 - 10 Recovery wait states 011 - 14 Recovery wait states 100 - 18 Recovery wait states Others (default Recovery wait states This change also affects Table 271, Flash Wait State Profile Programming. ® Affected Docs: Intel 80331 I/O Processor Developer’s Manual 62 Specification Update ...
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... IOP Attributes PCI Attributes ® Intel XScale core Local Bus Address FFFF E504H Bit Default RAS: Active to Precharge duration in MCLK periods 31:28 0H Equation 7: RAS = tRAS - 1 where tRAS is from SPD Reserved RP: Precharge Command Period in MCLK periods 26:24 000 2 Equation tRP - 1 where tRP is from SPD ...
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... Attributes PCI Attributes ® Intel XScale core Local Bus Address FFFF E504H Bit Default 07: Reserved. ODT Termination Value: Determines the termination value of the On Die Termination for both Banks (controlled by ODT[1:0]). Applies to DDR-II SDRAM memory type only. • 00 Disabled 05: • ohm • 10 150 ohm • ...
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... SPD WTRD: Write-to-Read turnaround period in MCLK periods. 03:00 0H Equation 14: WTRD = tCAS + tWTR + tREG where tREG = 1 for registered DIMM and 0 for unbuffered DIMM, tCAS and tWTR are from SPD. ® Affected Docs: Intel 80331 I/O Processor Developer’s Manual Specification Update ...
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... Documentation Changes 10. Power sequence timing Problem: Section 9.1 of the Intel requirement between VCC33 and VCC15, but does not mention any timing parameters. Workaround: The following are the power sequencing requirements that must be followed: 1. The 80331 requires that the VCC33 voltage rail be no less than 0.5 V below VCC15 (absolute voltage value) at all times during operations, including during system power-up and power-down ...
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... SBR0[6:0].” Workaround: The sentence should be changed to “If bank 1 is unpopulated, SBR1[6:0] and SBR1[31:30] should be programmed with a value equal to SBR0[6:0] and SBR0[31:30].” ® Affected Docs: Intel 80331 I/O Processor Developer’s Manual Specification Update ® Intel Documentation Changes 0 ...