MCIMX31LDVMN5D Freescale, MCIMX31LDVMN5D Datasheet - Page 26
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MCIMX31LDVMN5D
Manufacturer Part Number
MCIMX31LDVMN5D
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31LDVMN5D.pdf
(118 pages)
Specifications of MCIMX31LDVMN5D
Operating Temperature (min)
-20C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX31LDVMN5D
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCIMX31LDVMN5DR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1
Electrical Characteristics
4.3.5.1
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
timing parameters.
26
Values provided where applicable.
tskew1
tskew2
tskew3
tcable1
tcable2
tskew4
tskew5
tskew6
Name
ti_dh
ti_ds
tbuf
tsui
tco
tsu
thi
T
Bus clock period (ipg_clk_ata)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Hold time ata_iordy edge to ata_data (UDMA-in only)
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
Max buffer propagation delay
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Max difference in cable propagation delay without accounting for ground bounce
Timing Parameters
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Table 23. ATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Table 23
Freescale Semiconductor
Contributing Factor
peripheral clock
transceiver
transceiver
transceiver
frequency
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
15 ns
10 ns
shows ATA
cable
cable
cable
cable
cable
7 ns
5 ns
4 ns
7 ns
1