MCIMX353CJQ5C Freescale, MCIMX353CJQ5C Datasheet
MCIMX353CJQ5C
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MCIMX353CJQ5C Summary of contents
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... The i.MX35 supports connections to various types of external memories, such as SDRAM, mobile DDR, and DDR2, SLC and MCL NAND Flash, NOR Flash and © Freescale Semiconductor, Inc., 2010. All rights reserved. Document Number: MCIMX35SR2CEC Rev. 9, 08/2010 IMX35 ...
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... Asynchronous sample rate converter (ASRC) • 1-Wire • Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s) • Parallel display (primary up to 24-bit, 1024 x 1024) i.MX35 Applications Processors for Industrial and Consumer Products, Rev Freescale Semiconductor ...
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... MCIMX355AJQ4C i.MX355 MCIMX355AJQ5C i.MX356 MCIMX356AJQ4C i.MX356 MCIMX356AJQ5C i.MX353 MCIMX353CJQ5C i.MX353 MCIMX353DJQ5C i.MX357 MCIMX357CJQ5C i.MX357 MCIMX357DJQ5C 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: ...
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... Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes — Yes Yes — Yes Yes — Yes Yes — — Yes Freescale Semiconductor ...
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... The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1 caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace interfaces. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor LCD Display 1 NAND Camera Flash ...
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... The ARM1136JF-S processor core features are as follows: • Integer unit with integral EmbeddedICE • Eight-stage pipeline i.MX35 Applications Processors for Industrial and Consumer Products, Rev the nwells, and one that is lower than V DD ® technology (which enables direct execution of Java ™ logic SS Freescale Semiconductor ...
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... ARM interface ASRC Asynchronous SDMA sample rate converter i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor ™ Table 3. i.MX35 Core Brief Description Table 4. Digital and Analog Modules 1 Subsystem ARM1136 1-Wire provides the communication line to a 1-Kbit add-only platform memory ...
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... EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. Brief Description Freescale Semiconductor ...
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... GPU2D Graphics ARM processing unit 2Dv1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 1 Subsystem Connectivity The enhanced serial audio interface (ESAI) provides a full-duplex peripherals serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs ...
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... PLLs. This oscillator is designed to work in conjunction with an external 24.576-MHz crystal. Clock The signal from the external 24-MHz crystal is the source of the CLK24M signal fed into USB PHY as the reference clock and to the real time clock (RTC). Brief Description industry-standard, bidirectional suitable for 2 C system is Freescale Semiconductor ...
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... Connectivity The SSI is a full-duplex serial port that allows the processor peripherals connected communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the I 2 sound (I S) bus standard. The SSIs interface to the AUDMUX for flexible audio routing. ...
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... Tamper-detect logic is enabled by the bit of IOMUXC_GPRA[2]. After enabling the logic impossible to disable it until the next reset. Table 6. i.MX35 Chip-Level Conditions Characteristics Table/Location Table 7 on page 13 Table 8 on page 13 Table 9 on page 14 Detailed Description Table 6 for a quick reference Freescale Semiconductor ...
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... EMI WTDG, Timer, CCM, CSPI1 NANDF ATA, USB generic eSDHC1 CSI, SDIO2 JTAG LCDC, TTM, I2C1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor CAUTION Table 7 may cause permanent damage to the Table 7. Absolute Maximum Ratings Symbol 1 VDD max ...
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... V 1.75 — 3.6 V 3.17 3.3 3.43 V 3.17 3.3 3.43 V 3.17 3.3 3.43 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 1.4 — 1.65 V 1.4 — 1.65 V 3.0 3.6 3 –20 — –40 — Typ. Max. Units 5 10 MHz Freescale Semiconductor ...
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... MCU PLL is off. PER PLL is off. All clocks are gated off. OSC 24 MHz is on OSC audio is off RNGC internal osc is off i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 10. i.MX35 Power Modes QVCC (ARM/L2 MVDD/PVDD Peripheral) Typ. Max. ...
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... Wait until VDDn and NVCCx power supplies are stable + 32 μs. i.MX35 Applications Processors for Industrial and Consumer Products, Rev QVCC (ARM/L2 MVDD/PVDD Peripheral) Typ. Max. Typ. Max. µA — µA — 820 50 CAUTION NOTE OSC24M_VDD OSC_AUDO_VDD Typ. Max. µA — 24 Freescale Semiconductor ...
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... The power-up sequence in reverse order is recommended for powering down. However, all power supplies can be shut down at the same time. 4.4 Reset Timing There are two ways of resetting the i.MX35 using external pins: • Power On Reset (using the POR_B pin) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 17 ...
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... The table shows values representing maximum current numbers for the i.MX35 under worst case voltage and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to i.MX35 Applications Processors for Industrial and Consumer Products, Rev Freescale Semiconductor ...
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... MHz. Common supplies have been bundled according to the i.MX35 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX35 power supply requirements will be satisfied during startup and transient conditions. Freescale recommends that system current measurements be taken with customer-specific use-cases to reflect normal operating conditions in the end system ...
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... Natural convection Normal High 3.6 mA 7.2 mA — — — — Symbol Value Unit R 53 ºC/W eJA R 30 ºC/W eJA R 44 ºC/W eJMA R 27 ºC/W eJMA R 19 ºC/W eJB R 10 ºC/W eJCtop Ψ 2 ºC/W JT Max. 10 13.4 mA Freescale Semiconductor ...
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... Pull-down resistor (100 kΩ PD) External resistance to pull keeper up when enabled External resistance to pull keeper down when enabled i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Test Condition Voh Ioh = –1 mA NVCC – 0.15 0.8 × NVCC Ioh = specified drive ...
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... V 0.2 × NVCC –3.6 — — mA –7.2 –10.8 3.6 — — mA 7.2 10.8 0.7 × NVCC — NVCC + 0.3 V 0.2 × NVCC –0.3 — V — — 100 mV –100 — mV μA — — ±1 μA — — ±1 Freescale Semiconductor ...
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... Tri-state I/O supply current 4.8 I/O Pin AC Electrical Characteristics Figure 5 shows the load circuit for output pins. CL includes package, probe and jig capacitance i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Test Condition Voh loh = 5.7 mA Vol loh = 5.7 mA Ioh Max ...
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... NVCC 80% 20% 0V PA1 Max. Typ. Rise/Fall Units Rise/Fall — 1.30/1.77 2.02/2.58 V/ns 0.84/1.23 1.19/1.58 0.76/1.10 1.17/1.56 V/ns 0.41/0.62 0.63/0.86 0.40/0.59 0.60/0.83 V/ns 0.21/0.32 0.32/0. mA/ mA/ mA/ Max. Typ. Units Rise/Fall — 0.54/0.73 0.91/1.20 V/ns 0.35/0.50 0.60/0.80 Freescale Semiconductor ...
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... Table 18. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode Parameter Duty cycle Output pin slew rate (max. drive) Output pin slew rate (high drive) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor [NVCC = 1.65 V–1.95 V] (continued) Min. Symbol Test Condition Rise/Fall ...
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... Typ. Units Rise/Fall — 1.10/1.40 1.86/2.20 V/ns 0.90/1.10 1.53/1.73 0.73/0.99 1.20/1.50 0.71/0.98 1.16/1.40 V/ns 0.56/0.70 0.93/1.07 0.43/0.60 0.68/0.90 0.41/0.59 0.66/0.87 V/ns 0.32/0.35 0.51/0.59 0.23/0.33 0.36/0.48 62 148 mA/ns 65 151 42 102 mA/ns 44 107 21 52 mA/ Max. Typ. Units Notes Rise/Fall 40 — Freescale Semiconductor — ...
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... The typical value of Vox(ac) is expected to be about 0.5 × NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac) indicates the voltage at which the differential output signal must cross. Cload = 25 pF. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor [NVCC = 2.25 V–2.75 V] (continued) Test Min ...
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... V/ns 0.92/0.94 1.39/1.30 1.16/1.19 1.76/1.66 V/ns 0.61/0.63 0.93/0.87 0.59/0.60 0.89/0.82 V/ns 0.31/0.32 0.47/0.43 198 398 mA/ns 209 421 132 265 mA/ns 139 279 65 132 mA/ns 69 139 Max. Typ. Units Rise/Fall — — MHz 1.84/1.85 1.21/1.40 V/ns 1.03/1.05 0.70/0.75 Freescale Semiconductor ...
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... The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See the “External Signals and Multiplexing” chapter of the reference manual for more details. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Min. Symbol ...
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... Applications Processors for Industrial and Consumer Products, Rev CS2 CS3 CS3 CS2 CS3 CS2 CS3 CS2 Symbol t clk RISE/FALL t CSLH t SCS t HCS t Smosi t Hmosi t Smiso Table 26 lists the CS6 CS5 CS4 CS5 CS6 CS4 Min. Max. Units 60 — — ns — 7 — — — — — — ns Freescale Semiconductor ...
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... ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point access (TPA) that supports TRACECLK frequencies up to 133 MHz. Figure 9 depicts the TRACECLK timings of ETM, and Figure 9. ETM TRACECLK Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Symbol t Hmiso t SDRY Table 27 ...
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... Applications Processors for Industrial and Consumer Products, Rev Frequency dependent Figure 10. Trace Data Timing Diagram Min Table 29 still apply with respect to the falling edge of the Min. Max. Unit — — — ns — — Max. Unit — ns — ns Figure Figure 11, Figure Freescale Semiconductor 10. 12, ...
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... NFIO[7:0] Figure 11. Command Latch Cycle Timing DIagram NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 12. Address Latch Cycle Timing DIagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor lists the timing parameters. NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 ...
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... Table 30. NFC Timing Parameters Timing NFC Clock Cycle Symbol Min. Max. tCLS T – 4.0 ns — tCLH T – 5.0 ns — tCS T – 2.0 ns — tCH T – 1.0 ns — 1 Example Timing for ≈ NFC Clock 33 MHz Unit Min. Max. 26 — — — — ns Freescale Semiconductor ...
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... BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 1 (continued) Timing ...
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... Applications Processors for Industrial and Consumer Products, Rev Table 31 lists the timing parameters. WEIM Output Timing WE2 WE3 WE1 ... WEIM Input Timing BCLK WE18 WE20 WE22 WE24 WE26 WE27 Figure 15. WEIM Bus Timing Diagram Figure 15 depicts the WE5 WE7 WE9 WE11 WE13 WE15 WE17 Freescale Semiconductor ...
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... Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0. Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is set to maximum drive. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 31. WEIM Bus Timing Parameters Parameter 3 ...
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... Applications Processors for Industrial and Consumer Products, Rev Table 31 for specific control parameter settings. WE5 V1 V1 WE18 WE5 V1 WE7 WE9 WE15 WE12 WE13 V1 WE16 WSC = 1, EBWA = 1, EBWN = 1, LBN = 1 Next Address WE7 WE15 WE11 WE13 WE20, WE21 Next Address WE17 Freescale Semiconductor ...
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... EB[y] ECB DATA WE16 Figure 19. Synchronous Memory TIming Diagram for Burst Write Access— BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor WE5 Address V1 WE15 WE24, WE25 WE22, WE23 WE20, WE21 WE20, WE21 ...
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... WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7 i.MX35 Applications Processors for Industrial and Consumer Products, Rev WE5 Address V1 WE16 Write WE15 WSC = 7, LBA = 1, LBN = 1, LAH = 1 WE5 Address V1 WE14 WE15 WE10 WE17 Write Data WE7 WE9 WE13 WE20, WE21 Read Data WE18, WE19 WE7 WE11 WE13 Freescale Semiconductor ...
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... Figure 22. Asynchronous Memory Read Access CS[x] ADDR/ M_DATA WE LBA OE BE[y] MAXCO Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 32 help to determine timing parameters relative chip select (CS) Address V1 WE36 WE38 V1 WE43 MAXDI WE31 D(V1) Addr ...
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... Figure 25. Asynchronous A/D Mux Write Access i.MX35 Applications Processors for Industrial and Consumer Products, Rev WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr. V1 WE32A WE33 WE40A WE39 WE45 WE32 Next Address WE34 WE40 WE46 WE42 WE42 WE34 WE46 WE42 Freescale Semiconductor ...
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... CS[x] valid to BE[y] valid (read access) WE38 BE[y] invalid to CS[x] invalid (read access) WE39 CS[x] valid to LBA valid WE40 LBA invalid to CS[x] invalid i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor WE32 Address V1 WE40 WE36 WE38 V1 WE43 WE47 Figure 26. DTACK Read Access ...
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... Max Min (If 133 MHz is Unit supported by SoC (LBN + LBA + 1 – ns CSA) — 3 – WCSA ns — (WLBN + WLBA + ns ADH + 1 – WCSA) — 3 – CSN ns 6 – — — ns — (WBEA – CSA) ns — –3 + (WBEN – CSN – — — ns Freescale Semiconductor ...
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... SDRAM clock cycle time SD4 CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor through Table 42 list the timing parameters. SD1 SD2 SD4 SD3 ...
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... Applications Processors for Industrial and Consumer Products, Rev Parameter NOTE indicates SDRAM requirements. All output signals Symbol Min. Max. Unit tAH 1.8 — ns tAC — 6.47 ns tOH 1.2 — ns tRC 10 — clock Freescale Semiconductor ...
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... CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time SD7 Address hold time SD13 Data setup time SD14 Data hold time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor SD1 SD3 SD4 SD7 ROW / BA SD13 Parameter SD2 SD4 ...
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... SDRAM clock cycle time SD6 Address setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev NOTE SD1 SD2 SD3 SD10 SD10 ROW/BA Symbol Min. tCH 3.4 tCL 3.4 tCK 7.5 tAS 1.8 Max. Unit 4.1 ns 4.1 ns — ns — ns Freescale Semiconductor ...
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... ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. SDCLK CS RAS CAS WE ADDR BA CKE Don’t care Figure 30. SDRAM Self-Refresh Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 1 NOTE SD16 Symbol Min. Max. Unit tAH 1.8 — tRP 1 ...
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... CS, RAS, CAS, CKE, WE setup time i.MX35 Applications Processors for Industrial and Consumer Products, Rev NOTE Symbol tCKS DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 COL/BA Symbol Min. Max. Unit 1.8 — ns DDR2 DDR2-400 Unit Min Max 0.45 0. 0.45 0. 7.0 8 0.35 — Freescale Semiconductor ...
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... These values are for command/address slew rate of 1 V/ns and SDCLK, SDCLK_B differential slew rate of 2 V/ns. For different values, use the derating table. Table 38. Derating Values for DDR2–400, DDR2–533 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor DDR2-400 Symbol Min ...
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... DDR18 DDR18 Symbol t DS1(base) t DH1(base) t DSS t DSH t DQSS t DQSH t DQSL NOTE DDR20 DDR19 Data Data Data DDR2-400 Unit Min Max 0.025 — ns 0.025 — ns 0.2 — tCK 0.2 — tCK –0.25 0.25 tCK 0.35 — tCK 0.35 — tCK Freescale Semiconductor ...
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... Medium for SDCLK and High for Address and controls. SDCLK SDCLK_B DDR26 DQS (input) DQ (input) Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 39. DDR Single-ended Slew Rate NOTE DDR25 DDR24 DATA DATA DATA ...
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... Data Data Data Data SD17 SD18 SD18 Parameter DDR2-400 Unit Min Max — 0.35 ns 2.925 — ns –0.5 0.5 ns SD19 SD20 Data Data Data Symbol Min. Max. Unit tDS 0.95 — ns tDH 0.95 — ns tDSS 1.8 — ns tDSH 1.8 — ns Freescale Semiconductor ...
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... The timing parameters are similar to the ones used in SDRAM data sheets. Table 42 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor NOTE SD22 SD21 Data Data ...
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... Freescale Semiconductor ...
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... Periodically sampled and not 100% tested. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 1,2 Symbol Expression 5 — ...
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... SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out 89 FST (Bit) In FST (Word) In i.MX35 Applications Processors for Industrial and Consumer Products, Rev First Bit Figure 37. ESAI Transmitter Timing 83 87 Last Bit Freescale Semiconductor ...
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... FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed SD/SDIO card can reach 25 MHz. • HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO can reach 50 MHz. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor ...
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... SD4 SD2 SD5 SD3 SD6 SD7 SD8 Figure 39. eSDHCv2 Timing Parameter SD1 Symbols Min. Max. Unit 400 kHz 25/50 MHz 20/52 MHz PP f 100 400 kHz OD 7 — — — TLH t — THL t – — ns ISU 4 t 2.5 — Freescale Semiconductor ...
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... MII receive signal timings listed in FEC_RX_CLK (input) FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER Figure 40. MII Receive Signal Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 45 lists MII receive channel timings. Table 45. MII Receive Signal Timing 1 Table 45. ...
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... Applications Processors for Industrial and Consumer Products, Rev Table 46 lists MII transmit channel timings. Table 46. MII Transmit Signal Timing 1 Min. 5 — 35% 35% Table 46 Min. 1.5 Max. Unit — 65% FEC_TX_CLK period 65% FEC_TX_CLK period M8 Table 47 lists MII asynchronous Max. Unit — FEC_TX_CLK period Freescale Semiconductor ...
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... M13 FEC_MDIO (input) to FEC_MDC rising edge hold M14 FEC_MDC pulse width high M15 FEC_MDC pulse width low i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 47. M9 Table 48 Table 48. MII Transmit Signal Timing lists MII serial management Min. ...
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... Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX35 Applications Processors for Industrial and Consumer Products, Rev Table M14 M12 M13 website for details on FIR and MIR protocols. 48. M15 M10 M11 ® (Infrared Data Freescale Semiconductor ...
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... If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I specification) before the I2CLK line is released. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 2 C module module ...
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... LZ0P3714 (CCD) Motorola MC30300 (Python) National Semiconductor LM9618 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors have not been validated at the time of publication. 4.9.12.2 Functional Description There are three timing modes supported by the IPU. ...
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... Start of Frame nth frame SENSB_VSYNC SENSB_PIX_CLK SENSB_DATA[7:0] invalid Figure 46. Non-Gated Clock Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Active Line n+1th frame invalid 1st byte Section 4.9.12.2.2, “Gated Clock Figure n+1th frame invalid ...
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... Applications Processors for Industrial and Consumer Products, Rev that of a Motorola sensor. Some other sensors may have slightly Table 51 lists the timing parameters. 1/IP1 1/IP4 IP2 IP3 Symbol Fmck Min. Max. Units 0.01 133 MHz Tsu 5 — ns Thd 3 — ns Fpck 0.01 133 MHz Freescale Semiconductor ...
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... All figure parameters shown are programmable. The timing images correspond to inverse polarity i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor LINE 2 LINE 3 ...
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... Applications Processors for Industrial and Consumer Products, Rev IP7 IP6 IP9 Start of frame IP14 IP12 Figure 49 and Figure Symbol 1 Tdicp Tdicp (DISP3_IF_CLK_CNT_D + 1) × Tdicp Tdpcp (SCREEN_WIDTH + 1) × Tdpcp Tsw (H_SYNC_WIDTH + 1) × Tdpcp Thsw IP10 End of frame IP15 50. Value Units Freescale Semiconductor ...
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... DISPB_D3_DRDY other controls DISPB_D3_CLK IP16 DISPB_DATA Figure 51. Synchronous Display Interface Timing Diagram—Access Level i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Symbol BGXP × Tdpcp Thbi1 (SCREEN_WIDTH – BGXP – FW) × Tdpcp Thbi2 H_SYNC_DELAY × Tdpcp Thsd (SCREEN_HEIGHT + 1) × ...
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... Tdicu Tdhd Tdicp – Tdicd – 3.5 Tdicp – Tdicu Tcsu Tdicd – 3.5 Tdicu Table 54 1 Typ. Max. Units 3 – Tdicu Tdicd – Tdicu + 1.5 Tdicp – Tdicd + Tdicu + 1.5 — — — lists the timing parameters. The Freescale Semiconductor ...
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... IP23 CLS fall time IP24 CLS rise and PS fall time IP25 PS rise time IP26 REV toggle time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Horizontal timing D1 D2 IP21 1 DISPB_D3_CLK period IP23 IP25 IP26 Symbol (BGXP – 1) × Tdpcp Tsplr CLS_RISE_DELAY × ...
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... At a transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. i.MX35 Applications Processors for Industrial and Consumer Products, Rev Section 4.9.13.1.5, “Interface to Active Matrix Figure 53 Freescale Semiconductor depicts the ...
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... DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 308 309 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Odd Field Figure 53. TV Encoder Interface Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Pixel Data Timing 525 263 264 265 266 267 Odd Field ...
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... ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55, Figure 56, and Figure DISPB_Dn_WR and DISPB_Dn_RD signals. i.MX35 Applications Processors for Industrial and Consumer Products, Rev 57. These timing images correspond to active-low DISPB_Dn_CS, Figure 54, Freescale Semiconductor ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Burst access mode with sampling by CS signal 77 ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Burst access mode with sampling by WR/RD signals Freescale Semiconductor ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Burst access mode with sampling by CS signal 79 ...
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... Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the i.MX35 Applications Processors for Industrial and Consumer Products, Rev Burst access mode with sampling by ENABLE signal Freescale Semiconductor ...
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... Figure 59, Figure 61, Figure 60, and the system 80 and system 68k interfaces. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Figure 58 shows the timing of the parallel interface with WRITE OPERATION DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 Figure 62 depict timing of asynchronous parallel interfaces based on Table 55 lists the timing parameters at display access level ...
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... IP46,IP44 Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev IP28, IP27 IP31, IP29 read point Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 IP32, IP30 IP38 IP40 Freescale Semiconductor ...
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... IP37 DISPB_DATA (Input) DISPB_DATA (Output) IP46,IP44 Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor IP28, IP27 IP31, IP29 read point Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 ...
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... IP46,IP44 Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev IP28, IP27 IP31, IP29 read point IP38 Read Data IP39 IP47 IP45, IP43 IP42, IP41 IP36, IP34 IP32, IP30 IP40 Freescale Semiconductor ...
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... IP31 Write low pulse width IP32 Write high pulse width IP33 Controls setup time for read Tdcsr IP34 Controls hold time for read Tdchr i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor IP28, IP27 IP31, IP29 read point Read Data IP39 IP47 ...
Page 86
... Tdrp – 1.5 Tdrp 1 Typ. Max. — — — Tdrp – Tlbd – Tdicur – 1.5 — Tdicpr – Tdicdr – 1.5 — — Tdicpr + 1.5 Tdicpw + 1.5 Tdicdr + 1.5 Tdicur + 1.5 Tdicdw + 1.5 Tdicuw + 1.5 Tdrp + 1.5 Freescale Semiconductor Units ...
Page 87
... The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word whole burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers ( 2). i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 87 ...
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... DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) Figure 64. 4-Wire Serial Interface Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Input or output data Write Output data Read Input data 1 display IF clock cycle display IF clock cycle display IF clock cycle Freescale Semiconductor ...
Page 89
... DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS DISPB_D#_CS DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS Figure 65. 5-Wire Serial Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Write 1 display IF clock cycle Preamble Read 1 display IF clock cycle RW Preamble D7 D6 ...
Page 90
... IF DISPB_SER_RS clock cycle Figure 66. 5-Wire Serial Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev Write 1 display IF clock cycle Preamble Read clock cycle RW Preamble display IF clock cycle Output data 1 display IF clock cycle Input data Freescale Semiconductor ...
Page 91
... IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read Tdcsr i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 56 lists the timing parameters at display access level. IP49, IP48 IP50, IP52 ...
Page 92
... Tdrp – 1.5 Tdrp 1 Typ. Max. — — — — Tdrp – Tlbd – Tdicur – 1.5 — Tdicpr – Tdicdr – 1.5 — — Tdicpr + 1.5 Tdicpw + 1.5 Tdicdr + 1.5 Tdicur + 1.5 Tdicdw + 1.5 Tdicuw + 1.5 Tdrp + 1.5 Freescale Semiconductor Units ...
Page 93
... Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 parameters. MSHC_SCLK tSCLKr i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor depict the MSHC timings, and tSCLKc tSCLKwh tSCLKwl Figure 68. MSHC_CLK Timing Diagram Table 57 and Table 58 list the timing ...
Page 94
... MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Intput) Figure 69. Transfer Operation Timing Diagram (Serial) i.MX35 Applications Processors for Industrial and Consumer Products, Rev tSCLKc tBSsu tDsu tDd tBSh tDh Freescale Semiconductor ...
Page 95
... Table 57. Serial Interface Timing Parameters Signal MSHC_SCLK MSHC_BS i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor tSCLKc tBSsu tDsu tDd NOTE Parameter ...
Page 96
... Max. 25 — — — ns — — — — — — ns — Units Comment Min: 256 × 44.0 kHz MHz Typ: 256 × 48.0 kHz Typ: 512 × 48.0 kHz Max: 512 × 48.1 kHz Max: 512 × Fs PLL unlocked Freescale Semiconductor ...
Page 97
... Frequency MLBCLK rise time t mckr MLB fall time t mckf MLBCLK cycle time t mckc MLBCLK low time t mckl i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Min Typ Max — — 3 — 81 — — 40 — 31.5 37 — 30 35.5 — ...
Page 98
... Pulse” OW2 OW3 OW1 Symbol t 480 RSTL t 15 PDH t 60 PDL t 480 RSTH Units Comment ns PLL unlocked Note ns — ns — ns — Note DS2502 Tx OW4 Min. Typ. Max. Units 511 — µs — 60 µs — 240 µs 512 — µs Freescale Semiconductor ...
Page 99
... Figure 74. Read Sequence Timing Diagram ID Parameter OW7 Write 1/read low time OW8 Transmission time slot OW9 Release time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 62 lists the timing parameters. OW6 OW5 Symbol Min. t WR0_low t OW5 ...
Page 100
... When ata_buffer_en is asserted, the bus should drive from host to device. When i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 100 Parameter 1 1 SI2 SI1 Symbol Min. Max. Unit 1 S — 1.25 V/ns rise 1 S — 1.25 V/ns fall C — host Freescale Semiconductor ...
Page 101
... Maximum difference in cable propagation delay without accounting for ground bounce 1 Values provided where applicable. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 65. ATA Timing Parameters Description UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ ...
Page 102
... Applications Processors for Industrial and Consumer Products, Rev. 9 102 Table 66 lists the timing parameters for PIO read. Figure 76. PIO Read Timing Diagram Table 66. PIO Read Timing Parameters Value Controlling Variable time_1 time_2r time_3 If not met, increase time_2 — time_ax time_pio_rdx time_1, time_2r, time_9 Freescale Semiconductor ...
Page 103
... Avoid bus contention when switching buffer off by making toff long enough. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Table 67 lists the timing parameters for PIO write. Figure 77. PIO Write Timing Diagram Table 67. PIO Write Timing Parameters ...
Page 104
... Applications Processors for Industrial and Consumer Products, Rev. 9 104 Figure 79 shows timing for MDMA write. Figure 78. MDMA Read Timing Diagram Figure 79. MDMA Write Timing Diagram Value Table 68 lists the Controlling Variable time_m time_d time_k time_d, time_k time_d — time_d time_k time_d, time_k Freescale Semiconductor ...
Page 105
... UDMA-in burst. Figure 80. UDMA-In Transfer Starts Timing Diagram Figure 81. UDMA-In Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Value Figure 81 shows timing when the UDMA-in device terminates transfer, and ...
Page 106
... DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff large enough to avoid bus contention. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 106 Description Freescale Semiconductor Controlling Variable time_ack time_env tskew3, ti_ds, ti_dh ...
Page 107
... UDMA-out burst. Figure 83. UDMA-Out Transfer Starts Timing Diagram Figure 84. UDMA-Out Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Figure 84 shows timing when the UDMA-out device terminates transfer, and shows timing when the UDMA-out ...
Page 108
... T) – (tskew1 + tskew2) tcvh tcvh ton = time_on × T – tskew1 — ton toff = time_off × T – tskew1 toff i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 108 Value Freescale Semiconductor Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc — time_dzfs time_ss — ...
Page 109
... The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Signal Description US16 ...
Page 110
... Table 73 lists the SJC timing parameters. SJ1 SJ2 VM VIH VIL SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid Figure 87 depicts the SJC test clock depicts the SJC test access port, SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...
Page 111
... TCK low to output high impedance SJ8 TMS, TDI data set-up time SJ9 TMS, TDI data hold time SJ10 TCK low to TDO data valid i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 ...
Page 112
... Unit Min. Max. — 100 — — ns Timing Parameter Range Units Min. Max. — 0.7 ns — 1.5 ns — 24.2 — 31.3 — 1.5 ns — 13.6 — 18.0 40.0 — ns 16.0 — ns 16.0 — ns 40.0 — ns 16.0 — ns 16.0 — ns Freescale Semiconductor ...
Page 113
... SSI, respectively. • For internal frame sync operations using the external clock, the FS timing will be the same as that of Tx Data (for example, during AC97 mode of operation). i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor srckp srckpl srckph Figure 91 ...
Page 114
... Applications Processors for Industrial and Consumer Products, Rev. 9 114 Table 75 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 SS43 SS42 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 SS43 SS42 lists the timing parameters. SS3 SS12 SS15 SS18 SS19 SS3 SS12 SS15 SS18 SS19 Freescale Semiconductor ...
Page 115
... STXD rise/fall time SS42 SRXD setup before (Tx) CK falling SS43 SRXD hold after (Tx) CK falling SS52 Loading i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Parameter Internal Clock Operation Synchronous Internal Clock Operation Min. Max. Unit 81.4 — ...
Page 116
... Applications Processors for Industrial and Consumer Products, Rev. 9 116 Table 76 lists the timing parameters shown SS1 SS5 SS4 SS9 SS11 SS20 SS21 SS51 SS47 SS50 SS1 SS5 SS4 SS9 SS7 SS11 SS20 SS21 SS47 SS51 SS50 SS3 SS13 SS49 SS3 SS13 SS49 Freescale Semiconductor ...
Page 117
... Oversampling clock high period SS49 Oversampling clock rise time SS50 Oversampling clock low period SS51 Oversampling clock fall time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Parameter Internal Clock Operation Oversampling Clock Operation Min. Max. Unit 81.4 — ...
Page 118
... Applications Processors for Industrial and Consumer Products, Rev. 9 118 Table 77 SS22 SS25 SS26 SS29 SS31 SS37 SS38 SS45 SS44 SS22 SS26 SS25 SS29 SS31 SS37 SS38 SS45 SS44 lists the timing parameters. SS24 SS33 SS39 SS46 SS24 SS33 SS39 SS46 Freescale Semiconductor ...
Page 119
... CK high to STXD high impedance SS44 SRXD setup before (Tx) CK falling SS45 SRXD hold after (Tx) CK falling SS46 SRXD rise/fall time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Parameter External Clock Operation Synchronous External Clock Operation Min. Max. Unit 81.4 — ...
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... SS22 SS26 SS25 SS30 SS32 SS35 SS41 SS40 SS22 SS26 SS25 SS30 SS32 SS35 SS41 SS40 Parameter External Clock Operation lists the timing parameters. SS24 SS34 SS36 SS24 SS34 SS36 Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 121
... UART RS-232 serial mode transmit timing characteristics. UA1 Start TXD Bit 0 Bit 1 Bit (output) Figure 97. UART RS-232 Serial Mode Transmit Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Parameter UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Min. Max. ...
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... T ref_clk Table 80 lists Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA2 UA2 Max. Units 2 – 1/F + — baud_rate 1/(16 × baud_rate Table 81 lists UA3 UA3 STOP Possible Bit 6 Bit 7 BIT Parity Bit Freescale Semiconductor ...
Page 123
... DAT_SE0 bidirectional, 3-wire mode • DAT_SE0 unidirectional, 6-wire mode • VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Symbol Min. t 1/F TIRbit baud_rate T ref_clk (3/16) × (1/F ...
Page 124
... Figure 101 Signal Description Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high US1 US4 US7 and Figure 102 show the US3 US2 US8 Freescale Semiconductor ...
Page 125
... Out USB_VP1 In USB_VM1 In USB_RCV In Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US12 Figure 103. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Direction Min. Max. Unit Out — 5.0 Out — 5.0 Out — 5.0 Out 49 ...
Page 126
... Signal Description Transmit enable, active low Tx VP data when USB_TXOE_B is low Rx VP data when USB_TXOE_B is high Tx VM data when USB_TXOE_B low Rx VM data when USB_TXOE_B high Differential Rx data US16 Condition/ Unit Reference Signal — Figure 106 show the transmit Freescale Semiconductor ...
Page 127
... US19 Tx rise/fall time US20 Tx rise/fall time US21 Tx duty cycle US22 Tx overlap US26 Rx rise/fall time US27 Rx rise/fall time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor US20 US18 US22 US26 US28 US29 Signal Name Direction Min. USB_DAT_VP Out USB_SE0_VM ...
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... Tx VP data when USB_TXOE_B is low Tx VM data when USB_TXOE_B is low Rx VP data when USB_TXOE_B is high Rx VM data when USB_TXOE_B is high Differential Rx data US32 US30 US34 US34 Condition/ Max. Unit Reference Signal +4.0 ns USB_SE0_VM +2.0 ns USB_DAT_VP and Figure 108 show the US31 Freescale Semiconductor ...
Page 129
... USB_SE0_VM US34 Rx rise/fall time USB_VP1 US38 Rx rise/fall time USB_VM1 US39 Rx skew USB_VP1 US40 Rx skew USB_RCV US41 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor US38 US40 US39 US41 Signal Direction Min. Max. Out — 5.0 Out — 5.0 Out — ...
Page 130
... Package Information and Pinout This section includes the following: • Mechanical package drawing • Pin/contact assignment information i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 130 Freescale Semiconductor ...
Page 131
... MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch 5.1 See Figure 109 for the package drawing and dimensions of the production package. Figure 109. Production Package: Mechanical Drawing i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 131 ...
Page 132
... CSI_D10 V7 CSI_D11 T7 CSI_D12 R4 CSI_D13 V1 CSI_D14 R5 CSI_D15 Y5 CSI_D8 W5 CSI_D9 V3 CSI_HSYNC Y2 CSI_MCLK U3 CSI_PIXCLK Ball Location E14 W10 U9 V12 E16 Y10 T10 V10 T12 1 L16 F17 E19 B20 C19 E18 F19 1 V16 1 T15 1 W16 1 V15 1 U14 1 Y16 1 U15 1 W17 1 V14 1 W15 1 Y15 Freescale Semiconductor ...
Page 133
... D3_SPL 1 D3_VSYNC DE_B DQM0 DQM1 DQM2 DQM3 EB0 EB1 ECB EXT_ARMCLK EXTAL_AUDIO EXTAL24M FEC_COL FEC_CRS FEC_MDC i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID W2 CSI_VSYNC W1 CSPI1_MISO T4 CSPI1_MOSI V5 CSPI1_SCLK U5 CSPI1_SPI_RDY Y4 CSPI1_SS0 W4 CSPI1_SS1 V4 CTS1 G5 FEC_TDATA0 A2 FEC_TDATA1 D4 ...
Page 134
... Ball Location 1 L19 G16 G19 H16 H18 G20 H17 H19 G12 F13 F14 G14 P16 H14 J14 L14 M14 R10 P14 E20 V20 U19 T19 T18 M12 M15 N20 N16 P20 R13 P12 W11 Y9 N13 E15 U10 U18 U1 G1 C20 Freescale Semiconductor ...
Page 135
... SD2_DATA3 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID G7 RXD1 G8 RXD2 G9 SCK4 H9 SCK5 F10 SCKR G10 SCKT F11 SD0 ...
Page 136
... VSS F9 VSS F12 VSS R12 VSS G13 VSS H15 VSS J15 VSS A1 VSS Y1 VSS J8 VSTBY M8 WDOG_RST N8 XTAL_AUDIO J9 XTAL24M Ball Location P18 R20 R18 Y17 Y18 K10 P10 H11 H12 H13 J13 K13 L13 T17 A20 Y20 T9 Y12 V19 U20 Freescale Semiconductor ...
Page 137
... ATA_DA0 ATA_DA1 ATA_DA2 ATA_DATA0 ATA_DATA1 ATA_DATA10 ATA_DATA11 ATA_DATA12 ATA_DATA13 ATA_DATA14 ATA_DATA15 ATA_DATA2 ATA_DATA3 ATA_DATA4 ATA_DATA5 ATA_DATA6 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID A5 ATA_DATA7 D7 ATA_DATA8 F15 ATA_DATA9 D5 ATA_DIOR F6 ATA_DIOW B3 ATA_DMACK D14 ATA_DMARQ D15 ...
Page 138
... LD8 N3 LD9 Ball Location P13 M11 T11 Y11 U11 V11 K2 J5 M20 N17 L3 M1 D20 F20 G18 H20 J18 J16 J19 J17 J20 K14 K19 K18 K20 G17 K16 K17 K15 L19 G16 G19 H16 H18 G20 H17 H19 Freescale Semiconductor ...
Page 139
... NGND_SDIO NVCC_ATA NVCC_ATA NVCC_ATA NVCC_ATA NVCC_CRM NVCC_CSI NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NGND_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID C4 NVCC_EMI2 N11 NVCC_EMI2 W13 VSS Y13 NVCC_EMI3 W12 NVCC_JTAG P11 NVCC_LCDC G3 ...
Page 140
... B16 USBPHY1_VDDA_BIAS C14 USBPHY1_VSSA_BIAS A16 USBPHY2_DM A6 USBPHY2_DP B6 VDD D18 VDD E17 VDD Ball Location E12 E13 B17 A13 A10 C7 G15 U17 R17 P15 R15 Y7 R16 T16 M16 N19 P19 R19 N18 N14 N15 P17 P18 R20 R18 Y17 Y18 Freescale Semiconductor ...
Page 141
... VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS 1 Not available for the MCIMX351. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID L7 VSS N7 VSS R7 VSS F8 VSS R8 VSS F9 VSS F12 NVCC_EMI2 ...
Page 142
... PHY A0 1_V 1_R 1_V SSA REF DDA _BIA _BIA S S CSI_ CSI_ TRS VSS OSC OSC EXT VSY D11 TB 24M 24M AL24 NC _VS _VD CSI_ CSI_ SD1 SJC RTC OSC XTAL D14 D8 _DAT _MO K _AU 24M A1 D DIO_ VSS Freescale Semiconductor ...
Page 143
... TA2 N FEC FEC FEC FEC FEC NVC _RD _RD _RX_ _TX_ _CR C_AT ATA3 ATA1 ERR ERR S A i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor ATA_ EXT CSPI CLK GPI CAP SD2 CS0 _AR 1_MI O O3_ TUR ...
Page 144
... Product Documentation All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx. 7 Revision History Table 95 shows the revision history of this document. Note: There were no revisions of this document between revision 1 and revision 4 or between revision 6 and revision 7. Table 95. i.MX35 Data Sheet Revision History ...
Page 145
... SDRAM timing. Inserted DDR2 SDRAM timing. 0 10/2008 Initial public release i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor Substantive Change(s) 1, “Ordering Information.” 92, “Silicon Revision 2.1 Signal Ball Map Locations.” 94, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.” ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 146 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9 Freescale Semiconductor 147 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...