ATR0625PYQW Atmel, ATR0625PYQW Datasheet

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Features • 16-channel GPS Correlator – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (Stand-Alone, S/A off) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –142 dBm (Cold Start) – Tracking Sensitivity: –158 dBm ...

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... A-GPS (aiding also possible to store the configuration settings in an optional external EEPROM. The ATR0625P is manufactured using Atmel the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0625P provides a highly flexible and cost-effective solution for GPS applications ...

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Figure 1-1. ATR0625P Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM DBG_EN NTRST TDI TDO TCK TMS NRESET 4925G–GPS–06/08 ATR0625P ...

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Architectural Overview 2.1 Description The ATR0625P architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit ...

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Pin Configuration 3.1 Pinout Figure 3-1. Pinout QFN56 (Top View) Table 3-1. ATR0625P Pinout Pin Name QFN56 Pin Type CLK23 37 IN DBG_EN 8 IN (2) GND IN LDOBAT_IN 21 IN LDO_EN 25 IN LDO_IN 20 IN LDO_OUT 19 ...

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Table 3-1. ATR0625P Pinout (Continued) Pin Name QFN56 Pin Type P14 1 I/O P15 17 I/O P16 6 I/O P17 2 I/O P18 45 I/O P19 53 I/O P20 4 I/O P21 52 I/O P22 30 I/O P23 3 I/O ...

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Signal Description Table 3-2. ATR0625P Signal Description Module Name Function EBI BOOT_MODE Boot Mode Input TXD1 to TXD2 Transmit Data Output USART RXD1 to RXD2 Receive Data Input SCK1 to SCK2 External Synchronous Serial Clock USB_DP USB Data (D+) ...

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Table 3-2. ATR0625P Signal Description (Continued) Module Name Function TMS Test Mode Select TDI Test Data In TDO Test Data Out JTAG/ICE TCK Test Clock NTRST Test Reset Input DBG_EN Debug Enable CLOCK CLK23 Clock Input RESET NRESET Reset Input ...

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Setting GPSMODE0 to GPSMODE12 The start-up configuration of a ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the ...

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Sensitivity Settings Table 3-5. GPSMODE3 (Fixed PU Notes: For all GPS receivers the sensitivity depends on the integration time of the GPS signals. There- fore there is a trade-off between sensitivity and the time to ...

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Both USART ports and the USB port accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message ...

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The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM-Defaults): Table 3-11. Baud Rate (kBaud) Input Protocol Output Protocol Messages Information Messages (UBX INF or NMEA TXT) 3.3.4 USB Power Mode For correct response ...

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Table 3-13. Pin P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON Table 3-14. GPSMODE11 (Reset = PU Note: The Antenna Supervisor Software will be configured as follows: 1. Enable Control Signal 2. Enable Short ...

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External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL SC PURF PUXTO +3V (see Power Supply) (see Power Supply) GND NC: Not connected ATR0625P 14 SIGHI SIGLO CLK23 RF_ON NSLEEP NC ...

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Table 3-15. Recommended Pin Connection Pin Name Recommended External Circuit P0/NANTSHORT Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect P1/GPSMODE0 to VDD18 ...

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... ATR0625P in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0625P. The 32-bit RISC processor of the ATR0625P accesses the external memory with SPI (Serial Peripheral Interface). Atmel recommend to use 32 Kbit 1.8V serial EEPROM, e.g. the Atmel AT25320AY1-1.8. Figure 3-3. ...

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Power Supply The baseband IC is supplied with four distinct supply voltages: • VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory interface and the test pins and all GPIO-pins not mentioned in next ...

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The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply ...

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The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V. Figure 4-3. External Wiring Example ...

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Oscillator Figure 5-1. Crystal Connection 32.768 kHz 50 ppm can be derived from the crystal datasheet. Maximum value for pF. load load 6. Absolute Maximum Ratings Stresses beyond ...

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Electrical Characteristics If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions 1.1 DC supply voltage core DC supply voltage VDDIO 1.2 (1) domain ...

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Electrical Characteristics (Continued additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C. No. Parameters Test Conditions High-level output voltage I OH 1.23 VDDIO domain 3.0V Low-level output ...

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Power Consumption Table 9-1. Mode Sleep Shutdown Normal *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 10. ESD Sensitivity The ATR0625P is an ESD sensitive device. ...

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LDOBAT and Backup Domain The LDOBAT is a built in low dropout voltage regulator which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery ...

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Ordering Information Extended Type Number ATR0625P-PYQW ATR0625-EK1 ATR0625-DK1 14. Package QFN56 Package: QFN56 Exposed pad 6.5 x 6.5 Dimensions in mm Not indicated tolerances ±0. Drawing-No.: 6.543-5121.01-4 Issue: 1; 02.09.05 Moisture sensitivity level ...

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Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. 4925G-GPS-05/08 4925F-GPS-09/07 4925E-GPS-06/07 4925D-GPS-12/06 4925C-GPS-10/06 ATR0625P 26 History Table 3-1 “ATR0625P Pinout” ...

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