935270225557 NXP Semiconductors, 935270225557 Datasheet - Page 6

• Manufacturer Part Number: 935270225557
• Manufacturer: NXP Semiconductors

Specifications of 935270225557

• Pin Count: 64
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
7
1998 May 15
n.c.
TDO
TDI
TMS
V
AI22
V
AI21
V
AI12
V
AI11
V
AOUT
V
V
VREF
V
V
LLC
LLC2
CREF
RES
CE
V
V
HS
RTS1
SYMBOL
SSA2
DDA2
SSA1
DDA1
SSS
DDA0
SSA0
DDD5
SSD5
DDD4
SSD4
Enhanced Video Input Processor (EVIP)
PINNING
(L)QFP64
PIN
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
1
2
3
4
5
6
7
8
9
I/O/P
O
O
O
O
O
O
O
O
O
P
P
P
P
P
P
P
P
P
P
P
I
I
I
I
I
I
I
Do not connect.
Test data output for boundary scan test; note 1.
Test data input for boundary scan test; note 1.
Test mode select input for boundary scan test or scan test; note 1.
Ground for analog supply voltage channel 2.
Analog input 22.
Positive supply voltage for analog channel 2 (+3.3 V).
Analog input 21.
Ground for analog supply voltage channel 1.
Analog input 12.
Positive supply voltage for analog channel 1 (+3.3 V).
Analog input 11.
Substrate ground connection.
Analog test output; for testing the analog input channels.
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).
Ground for internal CGC.
Vertical reference output signal (I
signal (I
Digital supply voltage 5 (+3.3 V).
Ground for digital supply voltage 5.
Line-locked system clock output (27 MHz).
Line-locked clock
Clock reference output: this is a clock qualifier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is
provided on this pin.
Reset output (active LOW); sets the device into a defined state. All data outputs are
in high impedance state. The I
Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.
Digital supply voltage input 4 (+3.3 V).
Ground for digital supply voltage input 4.
Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64 s) via I
increments can be performed via I
Two functions output; controlled by I
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and
non-inverted R
a high state indicates that the internal horizontal PLL has locked.
2
C-bit COMPO = 1) (enabled via I
Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;
1
2
2
C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC
output (13.5 MHz).
6
2
C-bus is reset (waiting for start condition).
2
C-bit COMPO = 0) or inverse composite blanking
2
DESCRIPTION
C-bus bits HDEL1 and HDEL0.
2
C-bus bit RTSE1.
2
C-bus bit OEHV).
Product specification
SAA7111A