PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 492

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Unsigned 8-bit load with index
SYNTAX
FUNCTION
DESCRIPTION
32 bits, and writes the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a
single byte is loaded.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xd00, r20 = 2, [0xd02] = 0x22
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84
r70 = 0xd05, r30 = 0xfffffffc,
[0xd01] = 0x33
The
The result of an access by
The
[ IF rguard ] uld8r rsrc1 rsrc2 → rdest
if rguard then
rdest ← zero_ext8to32(mem[rsrc1 + rsrc2])
uld8r
uld8r
Initial Values
uld8r
operation loads the 8-bit memory value from the address computed by rsrc1 + rsrc2, zero extends it to
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
uld8r
uld8r r10 r20 → r80
IF r50 uld8r r40 r30 → r90
IF r60 uld8r r40 r30 → r100
uld8r r70 r30 → r110
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r80 ← 0x00000022
no change, since guard is false
r100 ← 0x00000084
r110 ← 0x00000033
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
uld8 ild8 uld8d ild8d
ATTRIBUTES
SEE ALSO
Result
ild8r
uld8r
dmem
194
4, 5
No
—
2
3
A-194