CY7C341B-35JC Cypress Semiconductor Corp, CY7C341B-35JC Datasheet
CY7C341B-35JC
Specifications of CY7C341B-35JC
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CY7C341B-35JC Summary of contents
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... LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341B allows used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips ...
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... MACROCELL 66 MACROCELL 67 MACROCELL 68 MACROCELL 69–80 LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELL 89–96 3, 24, 45, 66 (B5, G2, K7, E10 GND CY7C341B INPUT (C6) 84 INPUT (C7) 83 INPUT (L7) 44 INPUT (J7) 43 LAB G MACROCELL 97 46 (L6) MACROCELL 98 47 (L8) MACROCELL 99 48 (K8) MACROCELL 100 49 (L9) MACROCELL 101 ...
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... RSU DELAY LAD SYSTEM CLOCK DELAY t ICS CLOCK DELAY t IC LOGIC ARRAY DELAY t FD I/O DELAY t IO Figure 1. CY7C341B Internal Timing Model CY7C341B PGA Bottom View I/O I/O GND I/O INPUT I/O I/O I/O GND INPUT V I/O CC I/O INPUT INPUT I/O ...
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... Logic Array Blocks There are 12 logic array blocks in the CY7C341B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array ...
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... Test Conditions 1.0 MHz 0V 1.0 MHz OUT R1 464Ω 5V OUTPUT 250 Ω (b) 1.75V parameter refers to low-level TTL output current. OL CY7C341B [1] .............. −2.0V to +7.0V [1] ..................... − +25 mA [1] ................................................−2.0V to +7.0V [3] Ambient Temperature 0°C to +70°C –40°C to +85°C Min. Max. rise time 4.75(4.5) 5.25(5.5) [2] = – ...
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... Commercial [4] Commercial Commercial Commercial [6] Commercial [6] Commercial Commercial Commercial [7] Commercial Commercial [7] Commercial Over the Operating Range Description Commercial Commercial Commercial Commercial Commercial [4] Commercial [4] Commercial [8] Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial CY7C341B 7C341B-25 7C341B-35 Min. Max. Min. Max 12.5 8 12.5 62.5 40 ...
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... DEDICATED INPUTS OR REGISTERED FEEDBACK ASYNCHRONOUS CLOCK INPUT Document #: 38-03016 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS Over the Operating Range (continued) Description Commercial Commercial Commercial t /t PD1 PD2 CO1 AS1 CY7C341B 7C341B-25 7C341B-35 Min. Max Min. Max AWH AWL Page Unit ...
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... TO ANOTHER LAB Internal Synchronous SYSTEM CL OCK PIN t IN SYSTEM CLOCK AT REGISTER t RSU DATA FROM LOGIC ARRAY Document #: 38-03016 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS EXP t AWL RSU LATCH FD t PIA t ICS t RH CY7C341B LAC LAD t t COMB CLR PRE FD Page ...
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... RD DATA FROM LOGIC ARRAY OUTPUT PIN Ordering Information Speed (ns) Ordering Code 25 CY7C341B-25HC/HI CY7C341B-25JC/JI CY7C341B-25RC/RI 35 CY7C341B-35HC/HI CY7C341B-35JC/JI CY7C341B-35RC/RI Document #: 38-03016 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type H84 84-lead Windowed Leaded Chip Carrier J83 84-lead Plastic Leaded Chip Carrier ...
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... Package Diagrams 84-Leaded Windowed Leaded Chip Carrier H84 Document #: 38-03016 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C341B 51-80081-** Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 84-Lead Windowed Pin Grid Array R84 CY7C341B 51-85006-*A 51-80026-*B Page ...
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... Document History Page Document Title: CY7C341B 192-Macrocell MAX Document Number: 38-03016 Orig. of REV. ECN NO. Issue Date Change ** 106316 05/17/01 *A 113613 04/11/02 *B 122227 12/28/02 *C 213375 See ECN Document #: 38-03016 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS ® EPLD SZV Change from ecn #: 38-00137 to 38-03016 ...