IPPOSPHYP3 Altera, IPPOSPHYP3 Datasheet - Page 36

• Manufacturer Part Number: IPPOSPHYP3
• Manufacturer: Altera

Specifications of IPPOSPHYP3

• Lead Free Status / RoHS Status: Not Compliant

3–8
Parity Settings
POS-PHY Level 2 and 3 Compiler User Guide
1
■
The FIFO buffer width is the greater of the A bus width and the associated B bus
width.
Common B Clock
With MPHY configurations there is more than one ‘B’ interface in the MegaCore
function. Select this option to use a common clock and reset pins for all the ‘B’
interfaces that use the B clock option.
If you select this option, the ‘B’ interface clock and reset pins are labeled b_clk and
b_reset_n.
This section describes pass through mode and the parerr on error pin.
Pass Through Mode
In pass through mode any detected data parity errors on a sink interface are
regenerated on the source interface, even when there is a bus width change.
If a parity error is detected on a sink interface port that has a wider data width than its
corresponding source interface port, the parity error is generated on all output words
that correspond to the input word with an error.
Table 3–2
Table 3–2. Number of Errors Generated
If you are using the parity bit and the parity does not match the data, the MegaCore
function always detects the parity error.
For a source Atlantic interface, the par pin is an output that indicates the sink
interface has received parity errors.
For a sink Atlantic interface, the par pin is an input that sees either a one or a zero
depending on the incoming data’s parity value.
Data Width In
B Clock—the corresponding ‘B’ interface uses an internal dual clock FIFO buffer,
and is clocked by the corresponding ‘B’ interface clock pin
64
64
64
64
32
32
32
16
16
8
shows the number of errors generated per input error.
Data Width Out
16
32
64
16
32
16
8
8
8
8
Preliminary
Number of Errors Generated per Input Error
© November 2009 Altera Corporation
Chapter 3: Functional Description
8
4
2
1
4
2
1
2
1
1
Parameters