IPPOSPHYP3 Altera, IPPOSPHYP3 Datasheet - Page 45

• Manufacturer Part Number: IPPOSPHYP3
• Manufacturer: Altera

Specifications of IPPOSPHYP3

• Lead Free Status / RoHS Status: Not Compliant

Chapter 3: Functional Description
Interface Signals
Figure 3–15. Input/Output Specification
Global Interface
POS-PHY Level 3 Interface
© November 2009 Altera Corporation
Sink MegaCore Function
Source MegaCore Function
Interface
Interface
Source
Sink
'A'
'A'
Table 3–8
Table 3–8. Global Interface Description
The ‘A’ interface and each ‘B’ interface have independent resets, which are provided
to allow you to assert the reset asynchronously to its clock domain. They are not
intended to provide individual channel resets. If one channel needs a reset, all
channels must be reset. Deasserting the resets must be done synchronously to its clock
domain.
Additionally, IP Toolbench can connect the independent resets and clocks to a
common reset and clock (see
‘A’ interface signals are prefixed by a_; ‘B’ interface signals are prefixed by b1_, b2_,
and so on.
The interface direction is shown as either link to PHY, or PHY to link.
For a POS-PHY level 3 link-layer MegaCore function, the following rules apply:
treset_n Input
rreset_n Input
reset_n
clk
Note to
(1) POS-PHY clock signals are described in the relevant interface tables.
8 to 32
Signal
8 to 32
Table
describes the global interface signals.
Conversion
Conversion
Bus Width
Bus Width
(narrower)
3–8:
(wider)
Input
Input
Direction
8 to 64
8 to 64
Asynchronous reset for all flip-flops on the POS-PHY source tfclk
clock domain, active low. Can be asserted asynchronously, but must be
deasserted synchronously to tfclk.
Asynchronous reset for all flip-flops on the POS-PHY receive rfclk
clock domain, active low. Can be asserted asynchronously, but must be
deasserted synchronously to rfclk.
Asynchronous reset for the Atlantic interface, active low. Can be asserted
asynchronously, but must be deasserted synchronously to clk.
Clock, rising-edge active. The Atlantic interface uses single-edge
clocking. All signals are synchronous to clk, and master and slave are
in the same clock domain.
Preliminary
“Common B Clock” on page
8 to 64 bit
8 to 64 bit
FIFO
FIFO
(Note 1)
8 to 64
8 to 64
(1)
Conversion
Conversion
Bus Width
Bus Width
(narrower)
(wider)
Description
POS-PHY Level 2 and 3 Compiler User Guide
8 to 64
8 to 64
3–8).
Interface
Interface
'B'
'B'
3–17