AT94K05AL-25DQU Atmel, AT94K05AL-25DQU Datasheet - Page 44
AT94K05AL-25DQU
Manufacturer Part Number
AT94K05AL-25DQU
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25DQU.pdf
(204 pages)
Specifications of AT94K05AL-25DQU
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Industrial
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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General-purpose Register File
AT94KAL Series FPSLIC
Figure 4-5
Figure 4-5.
All the register operating instructions in the instruction set have direct- and single-cycle access
to all registers. The only exception is the five constant arithmetic and logic instructions SBCI,
SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load-
immediate constant data. These instructions apply to the second half of the registers in the reg-
ister file – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between
two registers or on a single-register apply to the entire register file.
As shown in
isters directly into the first 32 locations of the user Data Space. Although not being physically
implemented as SRAM locations, this memory organization provides great flexibility in access of
the registers, as the X, Y and Z registers can be set to index any register in the file.
The 4 to 16
eral data are implemented starting at address $0060 as follows:
Addresses beyond the maximum amount of data SRAM are unavailable for write or read and will
return unknown data if accessed. Ghost memory is not implemented.
Working Registers
General-purpose
shows the structure of the 32 x 8 general-purpose working registers in the CPU.
Kbytes
Figure 4-5
AVR CPU General-purpose Working Registers
of data SRAM, as configured during FPSLIC download, are available for gen-
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
each register is also assigned a data memory address, mapping the reg-
7
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
. . .
. . .
R0
R1
R2
$0060 : $0FFF
$0060 : $1FFF
$0060 : $2FFF
$0060 : $3FFF
0
Addr.
$00
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
AVR X-register Low Byte
AVR X-register High Byte
AVR Y-register Low Byte
AVR Y-register High Byte
AVR Z-register Low Byte
AVR Z-register High Byte
1138I–FPSLI–1/08
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