AT94K10AL-25BQC Atmel, AT94K10AL-25BQC Datasheet - Page 158

• Manufacturer Part Number: AT94K10AL-25BQC
• Manufacturer: Atmel

Specifications of AT94K10AL-25BQC

• Device System Gates: 10000
• Propagation Delay Time: 12.7ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

4.31
4.31.1
4.31.1.1
158
I/O Ports
AT94KAL Series FPSLIC
PortD
PortD as General Digital I/O
All AVR ports have true read-modify-write functionality when used as general I/O ports. This
means that the direction of one port pin can be changed without unintentionally changing the
direction of any other pin with the SBI and CBI instructions. The same applies for changing drive
value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
PortD is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for the PortD, one each for the Data Register
– PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins –
PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the
Data Direction Register are read/write.
The PortD output buffers can sink 20 mA. As inputs, PortD pins that are externally pulled Low
will source current if the pull-up resistors are activated.
PortD Data Register – PORTD
PortD Data Direction Register – DDRD
PortD Input Pins Address – PIND
The PortD Input Pins address – PIND – is not a register, and this address enables access to the
physical value on each PortD pin. When reading PORTD, the PortD Data Latch is read, and
when reading PIND, the logical values present on the pins are read.
PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If
DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is config-
ured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull-up resistor
is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or the pin has to
be configured as an output pin. The port pins are input with pull-up when a reset condition
becomes active, even if the clock is not running, see
Bit
$12
Read/Write
Initial Value
Bit
$11
Read/Write
Initial Value
Bit
$10
Read/Write
Initial Value
7
PORTD7
R/W
1
7
DDD7
R/W
0
7
PIND7
R
Pull1
6
PORTD6
R/W
1
6
DDD6
R/W
0
6
PIND6
R
Pull1
5
PORTD5
R/W
1
5
PIND5
R
Pull1
5
DDD5
R/W
0
4
PORTD4
R/W
1
Pull1
4
DDD4
R/W
0
4
PIND4
R
3
DDD3
R/W
0
3
PIND3
R
Pull1
3
PORTD3
R/W
1
Table
4-34.
2
PIND2
R
Pull1
2
DDD2
R/W
0
2
PORTD2
R/W
1
1
PIND1
R
Pull1
1
DDD1
R/W
0
1
PORTD1
R/W
1
Pull1
0
DDD0
R/W
0
0
PIND0
R
0
PORTD0
R/W
1
1138I–FPSLI–1/08
PIND
DDRD
PORTD