XCM20014IBMN Freescale, XCM20014IBMN Datasheet
XCM20014IBMN
Specifications of XCM20014IBMN
Related parts for XCM20014IBMN
XCM20014IBMN Summary of contents
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... Specifications and information herein are subject to change without notice. MOTOROLA, INC. 2002 Rev 4.1 15Aug2002 For More Information On This Product, C interface 2 C interface. Programmable digital signal processing blocks Go to: www.freescale.com Order this document by MCM20014/D MCM20014 ImageMOS ImageMOS Ordering Information Device Package XCM20014IBMN 48 CLCC-IB Monochrome XCM20014IBBN 48 CLCC-IB Color ...
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... Temperature Operating Range: 0-40 MOTOROLA 2 Sensor Interface Block I2C Serial Interface 10 Bit Global Global Gain Offset ADC o C For More Information On This Product, Go to: www.freescale.com MCLK INIT STBY SYNC SCLK SDATA Post ADC ADC(9:0) HCLK Bad Pixel Replace VCLK Noise Companding SOF MCM20014 ...
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... Post ADC Processing (Bad Pixel, Companding.) V refp V refm Analog Circuits V cm Digital Logic I bias CVBG2 CVBG1 EXTRES Figure 2. MCM20014 Detailed Block Diagram For More Information On This Product, Go to: www.freescale.com TEST_IN_7 TEST_IN_8 TEST_IN_9 DVDD1 SYNC 512 704 INIT 27 STDBY 26 SDATA I2C Serial ...
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... The use of pinned photodiodes (3) and pro- prietary transfer gate devices in the photoelements 1. ImageMOS is a Motorola trademark 2. Advanced CMOS Imager is a Kodak trademark 3. Patents held jointly by Motorola and Kodak For More Information On This Product, Go to: www.freescale.com 2 C serial TM (1) sensor comprises a TM ...
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... Microlenses yield greatest benefits when the main lens has a high F number caution, unoptimized F numbers can lead to optical aberrations hence, care should be taken when For More Information On This Product, Go to: www.freescale.com Figure 4), however, facility to produce Figure 5. The ...
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... Interest’ (WOI). The window of interest can be defined anywhere on the pixel array at any size. The user provides the upper-left pixel location and the size in both rows and columns to define the WOI. The For More Information On This Product, Go to: www.freescale.com Capture Mode 31. Sub-sample 32. ...
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... T is the minimum amount of time required to perform fc a frame clamp with timing overhead and is defined as: for a pictorial descrip (719 + shs fc For More Information On This Product, Go to: www.freescale.com vcw[13:0] WOI Pointer (wcp,wrp) Window of Interest (WOI) WOI Column Width (wcw) Virtual Frame * for T ...
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... The dark pixel sample period is automati- cally controlled internally and it is set to skip the first 2 dark rows and then sample the next dark row. When For More Information On This Product, Go to: www.freescale.com CDSP1 S/H1 AMP CDSP2 S/H2 implementation ...
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... This is accomplished via the Tile Configuration Register, (Table 7), on page 20 the Color Tile Row Definition registers Column DOVA DC Table 11). For More Information On This Product, Go to: www.freescale.com Figure 12.) are (Table 3 6). For the default Bayer configuration of Figure 4, the Color Gain Register ...
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... For other choices, the I/O relationship is kept 1 certain breakpoint. There onwards a straight line equation is used to transform the remaining input values. For More Information On This Product, Go to: www.freescale.com and Table 13). This feature is used (Table 21 respectively) while the functions them- Post ADC Control Register, 29 ...
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... By utilizing this mode, the user may reduce dynamic power consumption from 400mW, in the active process- ing, 13 Million Samples per Second mode, to < the standby mode (note that dynamic power con- sumption is also reduced in slower conversion speed applications). For More Information On This Product, Go to: www.freescale.com h Data IN (10-bit) 1023 MOTOROLA 11 ...
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... Figure 17 and forms with the Internal Timing Control Register loaded with For More Information On This Product, Go to: www.freescale.com allows into this address loca bit res of the Power Configuration Regis- depicts the power savings that can Ω ...
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... Row Time = vcw + 31 d row 12 Valid Pixel Data Figure 16. CFCM Default Line Waveform Frame Time = 525 row times Row Time = 800 MCLKs WOI = 640 Columns x 480 Rows starting at row 12, column 48 For More Information On This Product, Go to: www.freescale.com Sub-sample to1 . b row 13 h MOTOROLA 13 ...
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... Valid Pixel Data + 1) * Row Time d Odd Field Marker Pulse Width = 4 * MCLK period Positioned at mid-point of final Row Time of Field Blanking For More Information On This Product, Go to: www.freescale.com + 19 d row 13 h Standard Frame Timing (Figure 18) Frame Blanking For even vrd : blank time = vrd ...
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... T = (16 * sint ) + vcw + 52 for vcw > 718 Row Time = vcw row 12 Pixel Array Values Figure 22. SFCM Default Line Waveform For More Information On This Product, Go to: www.freescale.com Figure Figure 24 depict the same SFCM wave row 13 Valid Pixel Data MOTOROLA 15 ...
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... Row Time = vcw = 749 + 800 MCLK’s row shs d d Address Range Each block con Table 1. I For More Information On This Product, Go to: www.freescale.com h + shr + shs + row 13 Valid Pixel Data h Block Name - 0F Analog Register Interface Global Gain Offset Calibration Post ADC ...
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... Register Function (Green of Green-Red (Red) (Blue) (Green of Blue-Green Unused Unused Unused 2 Table Address Assignments For More Information On This Product, Go to: www.freescale.com Defa Ref. Shadow ult Table ed? 02 Table 3, page 19 Yes h 02 Table 4, page 19 Yes ...
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... Internal Timing Control Register Table 2. I MOTOROLA 18 Register Function Unused Unused Unused Factory Use Only Unused 2 C Address Assignments (Continued) For More Information On This Product, Go to: www.freescale.com Defa Ref. Shadow ult Table ed? 01 Table 22, page Table 23, page Table 24, page 31 Yes h 00 Table 25, page 32 Yes ...
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... Table 3. DPGA Color 1 Gain Register DPGA Color 2 Gain Code Red cg2[5] cg2[4] cg2[3] Description ) d Table 4. DPGA Color 2 Gain Register For More Information On This Product, Go to: www.freescale.com Color Tile Configuration Table 5, and Table 6. Gain for each individual Default lsb (0) cg1[2] cg1[1] cg1[0] ...
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... CFA option has been ordered. This register can be configured to any pattern combina- Color Tile Config- tion rows and columns. Color Tile Configuration nc[1] Description Table 7. Color Tile Configuration Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) cg3[2] cg3[1] cg3[0] Reset State xx 000010 ...
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... Color Tile Row 1 Definition Green - Red Row r1c3[0] r1c2[1] Description Table 8. Color Tile Row 1 Definition Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) nc[0] nr[1] nr[ the Color Gain Register addresses are as ): green pixel of a green-red row ...
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... Color Tile Row 2 Definition Blue - Green Row r2c3[0] r2c2[1] Description Table 9. Color Tile Row 2 Definition Register Color Tile Row 3 Definition Unused r3c3[0] r3c2[1] Description Table 10. Color Tile Row 3 Definition Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) r2c2[0] r2c1[1] r2c1[0] Reset State ...
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... When adjusting these values, the user should keep the voltage range Table 13, centered around 1.25V. Voltage Reference “Negative” Code nrv[5] nrv[4] nrv[3] Description ) d For More Information On This Product, Go to: www.freescale.com Default lsb (0) r4c2[0] r4c1[1] r4c1[0] Reset State ...
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... Description = Internal Resistor = External Resistor = Output Data Bus enabled = Output Data Bus in Tristate = Soft Standby inactive = Soft Standby active Table 14. Power Configuration Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) prv[2] prv[1] prv[0] Reset State 10000000 b (1 ...
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... The default value for this register results in unity gain. Global Gain gg[5] gg[4] gg[3] Description ) d Table 16. DPGA Global Gain Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) clt ssr sit Reset State xxxxx ...
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... Description = Positive Offset = Negative Offset d Table 17. Column DOVA DC Register 18, is used using their own algorithm and load this data via the I bus as defined in this section. For More Information On This Product, Go to: www.freescale.com . h Default lsb (0) cdd[2] cdd[1] cdd[0] Reset ...
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... Therefore, each code value in the DOVA RAM repre- sents 2 code values in the 10-bit ADC output. Column DOVA RAM cor[3] Description = Positive Offset = Negative Offset Table 19. Column DOVA RAM For More Information On This Product, Go to: www.freescale.com Default lsb (0) fuo cntr cal Reset State 000 ) 0 ...
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... This forc- d White Pixel hence a white b - 1023 can d d For More Information On This Product, Go to: www.freescale.com Default lsb (0) cor[2] cor[1] cor[0] auto i.e. 010111 should d ...
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... Please see Post ADC Control wpe bpe cps Description = Compander Disabled = Compander Enabled Table 23. Post ADC Control Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) wpt[2] wpt[1] wpt[0] Reset State 11111110 b ...
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... The he bit is used to determine whether HCLK is output continously or for the WOI pixels only. The default is WOI only. The hp bit is used to define whether HCLK is active high or low. HCLK is active high in default. for For More Information On This Product, Go to: www.freescale.com Default lsb (0) cpb[2] ...
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... MCLK rate. The row sampling rate is defined by rf[1:0] while the col- umn sampling rate is defined by cf[1:0]. The pixel array is fully sampled in default. For More Information On This Product, Go to: www.freescale.com Default lsb (0) ...
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... Table 25. Sub-sample Control Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) rf[0] cf[1] cf[0] Reset State ...
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... Full Row Wide b Table 26. SOF Control Register VCLK Control vck[5] vck[4] vck[3] Description = 1 MCLK Wide MCLKs Wide MCLKs Wide b = Full Row Wide b Table 27. VCLK Control Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) sof[2] sof[1] sof[0] Reset State 11 b 000000 b Default ...
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... The user should be careful to create a WOI that con- tains active pixels only. There is no logic in the sensor (Table 29 and Table (Table and Table 30), (Table 31 and For More Information On This Product, Go to: www.freescale.com to this register; thus h Default lsb (0) shr[2] shr[1] shr[0] Reset State 0110 ...
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... Table 29. WOI Row Pointer MSB Register WOI Row Pointer LSB wrp[5] wrp[4] wrp[3] Description Table 30. WOI Row Pointer LSB Register WOI Column Pointer MSB Description Table 31. WOI Column Pointer MSB Register For More Information On This Product, Go to: www.freescale.com Default lsb ( wrp[8] Reset State xxxxxxxx (Table 30 Default 0C h ...
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... Description Table 33. WOI Row Depth MSB Register WOI Row Depth LSB wrd[5] wrd[4] wrd[3] Description + 1. d Table 34. WOI Row Depth LSB Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) wcp[2] wcp[1] wcp[0] Reset State (Table 00110000 (col. 48) Default ...
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... The Virtual Frame must be 1 row and 6 columns larger than the WOI. The Virtual Frame completely defines the integration time in CFCM. Any changes to the WOI or how the WOI is sampled has no effect on integration time. For More Information On This Product, Go to: www.freescale.com Default ...
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... Table 37. Integration Time MSB Register Integration Time ISB sint[12] sint[11] cint[12] cint[11] Description (Table 39) Registers, forms the 20-bit Integra- Table 38. Integration Time ISB Register For More Information On This Product, Go to: www.freescale.com Default lsb (0) sint[18] sint[17] sint[16] Reset State xxxx (Table 38) and ...
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... Registers, forms the 20-bit Integra MCLKperiod row Table 39. Integration Time LSB Register CFCM Virtual Frame Row Depth MSB vrd[12] vrd[11] Description For More Information On This Product, Go to: www.freescale.com Default lsb (0) sint[2] sint[1] sint[0] cint[2] cint[1] cint[0] Reset State (Table 37) and ...
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... Description minimum = wrd + CFCM Virtual Frame Column Width MSB vcw[12] vcw[11] Description 43) Register, forms the 14-bit Virtual Frame Column Width For More Information On This Product, Go to: www.freescale.com Default lsb (0) vrd[2] vrd[1] vrd[0] Reset State (Table 00001100 (525 rows) Default ...
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... SCLK is low as shown in data on the SDATA line is valid on the High to Low sig- nal transition on the SCLK line. The R/W bit following the 7-bit tells the slave the desired direction of data Figure transfer: For More Information On This Product, Go to: www.freescale.com Default lsb (0) ...
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... R/W bit is For More Information On This Product, Go to: www.freescale.com Figure 25). Figure 26, a Repeated START signal is be- MCM20014 ...
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... Register Address • MCM20014 slave sends acknowledgment by forc- ing the SDATA Low during the 9th clock after re- ceiving the data to be written into the Register Address • Master transmits STOP to end the write cycle For More Information On This Product, Go to: www.freescale.com LSB ...
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... C Bus Address Read Ack Bit fromMCM20014 The MCM20014 transitions from a “SLAVE-transmitter” LSB to a “SLAVE-receiver” after the register data is sent Stop Signal from MASTER Figure 26. READ Cycle using Bus For More Information On This Product, Go to: www.freescale.com 103 LSB Ack Repeated Bit ...
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... Condition Min, V Min = 0 Min Min Min Output = High Impedance 0mA, V out in For More Information On This Product, Go to: www.freescale.com Value Unit -0.5 to 3 ±50 mA ±100 mA -65 to +150 °C 300 °C Min Max Unit 3.0 3 ° °C ...
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... Typ 0. Typ 0 CMOS IMAGE SENSOR CHARACTERISTICS Typ 3.0 0.2 0.4 0.9995 11.5 200 ) that the device can be exposed to before blooming of the pixel will sat For More Information On This Product, Go to: www.freescale.com Typ Unit 400 200 mW Unit Notes µJ/ pk-pk 3 Unit Notes µ ...
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... INL & DNL test limits are adjusted to compensate for the effects of the LRC, DOVA and DPGA stages between teh EXT_VINS inpt and the input of the ADC. MCM20014 GENERAL Typ 70 50 Analog to Digital Converter (ADC) Min 8 For More Information On This Product, Go to: www.freescale.com Unit Notes - 1 e rms dB Typ Max Units ...
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... MOTOROLA 48 6 TIMING SPECIFICATIONS (see Characteristic SCLK low period = (0.2)*VDD (.8)*VDD SDATA hold time SCLK high period SDATA setup time Figure 27 Bus Timing Diagram For More Information On This Product, Go to: www.freescale.com Figure 27) Min Max Unit 50 400 KHz MCLK MCLK 8 µs - ...
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... SYNC SOF t dvclk VCLK t drhclk HCLK t dadc ADC[9:0] t dblank BLANK MCM20014 Figure 28) Characteristic t hsync t dsof t dfhclk Figure 28. Pixel Data Bus Timing Diagram For More Information On This Product, Go to: www.freescale.com Min Typ Max Unit 1 11.5 13.5 MHz 3 3 21.5 ns 8.5 13 7.5 13 ...
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... SOF ADC9 ADC8 I 48 ADC7 Top-View Figure 29. MCM20014 Pinout Diagram For More Information On This Product, Go to: www.freescale.com Pin Description Power Type I2C Serial Clock I/O I2C Serial Data I/O Power Down Standby Enable I Sensor Intialize I Three State Ouput Enable I Sensor Sync Signal ...
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... G H 0.033 J 0.555 K 0.525 Figure 30. 48 Terminal ceramic leadless chip carrier (bottom view) MCM20014 Max 0.572 0.545 0.120 0.024 0.083 0.095 0.040 BSC 0.047 0.572 0.545 0.028 REF 0.028 REF 0.028 REF For More Information On This Product, Go to: www.freescale.com MOTOROLA 51 ...
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... Die Placement Positional Tolerance 200µm (7.9mils) Note: Pictured elements are shown for reference, not to scale. .200" Ref Notes: 1. Dimensions are in inches. 2. Interpret dimensions and tolerances per ASME Y14.5-1994 For More Information On This Product, Go to: www.freescale.com MCM20014 ...
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... Maximum possible variation Lid Seal thickness Die For More Information On This Product, Go to: www.freescale.com Die Lid to Die Surface to Dimensional Seating Plane Analysis G H 31.82 12.17 50.25585 52.39 28.74 61.33065 42.11 20.46 55 ...
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... Motorola, Inc. Motorola, Inc Equal JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Go to: www.freescale.com MFax is a trademark of Motorola, Inc. MCM20014 ...