XCM20014IBMN Freescale, XCM20014IBMN Datasheet - Page 43

• Manufacturer Part Number: XCM20014IBMN
• Manufacturer: Freescale
• Type: CMOSr

Specifications of XCM20014IBMN

• Sensor Image Color Type: Color
• Sensor Image Size Range: 250,920 to 480,000Pixels
• Sensor Image Size: 640x480Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 40C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MCM20014
6.8 I 2 C Bus Clocking and Synchronization
Open drain outputs are used on the SCLK outputs of all
master and slave devices so that the clock can be syn-
chronized and stretched using wire-AND logic. This
means that the slowest device will keep the bus from
going faster than it is capable of receiving or transmit-
ting data.
After the master has driven SCLK from High to Low, all
the slaves drive SCLK Low for the required period that
is needed by each slave device and then releases the
SCLK bus. If the slave SCLK Low period is greater than
the master SCLK Low period, the resulting SCLK bus
signal Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the de-
vice with the longest Low period. Also, this method can
be used by the slaves to slow down the bit rate of a
transfer. The master controls the length of time that the
SCLK line is in the High state. The data on the SDATA
line is valid when the master switches the SCLK line
from a High to a Low.
Slave devices may hold the SCLK low after completion
of one byte transfer (9 bits). In such case, it halts the bus
clock and forces the master clock into wait states until
the slave releases the SCLK line.
SDATA
SCLK
Signal
Start
SDATA
SCLK
AD7 AD6 AD5 AD4 AD3 AD2 AD1
MSB
MSB
“0”
1
D7
1
Data to write MCM20014 Register
MCM20014 I
“1”
2
D6 D5
2
“1”
3
3
Freescale Semiconductor, Inc.
“0”
4
2
For More Information On This Product,
4
D4
C Bus Address
Figure 25. WRITE Cycle using I 2 C Bus
“0”
5
D3 D2
5
“1”
6
6
Go to: www.freescale.com
LSB
“1”
7
D1 D0
7
Write
LSB
8
MCM20014
8
MCM20014
from
Ack
Bit
from
Ack
9
9
Bit
MSB
D7
6.9 Register Write
Writing the MCM20014 registers is accomplished with
the following I 2 C transactions (see
•
•
•
•
•
•
•
•
1
Signal
Stop
MCM20014 Register Address
Master transmits a START
Master transmits the MCM20014 Slave Calling Ad-
dress with “WRITE” indicated (BYTE=66
01100110
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock, if the Call-
ing Address was received
Master transmits the MCM20014 Register Address
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the Register Address
Master transmits the data to be written into the reg-
ister at the previously received Register Address
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the data to be written into the Register
Address
Master transmits STOP to end the write cycle
D6 D5
2
3
4
D4
b
)
5
D3
D2 D1
6
7
LSB
8
D0
MCM20014
from
Ack
Bit
9
Figure
25):
h
, 102
MOTOROLA
d
,
43