MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 36

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PLL-Generated Master Clock
Figure 13:
PLL Setup
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
PLL-Generated Master Clock
Note:
Note:
1. Bring the MT9P031 up as normal, make sure that
2. Set PLL_m_Factor, PLL_n_Divider, and PLL_p1_Divider based on the desired input
The D
should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to
these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of
PIXCLK is inverted from that shown in Figure 8 on page 13. In addition, if the pixel clock
has been divided by Divide_Pixel_Clock, it can be shifted relative to the other outputs by
setting Shift_Pixel_Clock.
The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to
multiply the prescaler output, and another divider stage to generate the output clock.
The clocking structure is shown in Figure 13. PLL control registers can be programmed
to generate desired master clock frequency.
EXTCLK
The MT9P031 has a PLL which can be used to generate the pixel clock internally.
To use the PLL:
f
where
M = PLL_m_Factor
N = PLL_n_Divider + 1
P1 = PLL_p1_Divider + 1
PIXCLK = (
The PLL control registers must be programmed while the sensor is in the software
Standby state. The effect of programming the PLL divisors while the sensor is in the
streaming state is undefined.
and then power on the PLL by setting Power_PLL (R0x10[0] = 1).
(
achieve the desired
If P1 is odd (that is, PLL_p1_Divider is even), the duty cycle of the internal system
clock will not be 50:50. In this case, it is important that either a slower clock is used or
all clock enable bits are set in R101.
f
EXTCLK) and output (
OUT
PLL_n_divider +1
, LV, FV, and STROBE outputs are launched on the rising edge of PIXCLK, and
f
EXTCLK × M) / (N × P1)
Pre PLL
(PFD)
Div
PLL Input Clock
N
f
PIXCLK using this formula:
f
PIXCLK) frequencies. Determine the M, N, and P1 values to
PLL_m_factor
36
Multiplier
(VCO)
PLL
M
PLL Output Clock
MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
PLL_p1_divider +1
Output
Div 1
PLL
f
P1
EXTCLK is between 6 and 27 MHz
Aptina reserves the right to change products or specifications without notice.
©2005 Aptina Imaging Corporation. All rights reserved.
SYSCLK (PIXCLK)
Features