CYII5SC1300AB-QWC Cypress Semiconductor Corp, CYII5SC1300AB-QWC Datasheet - Page 20

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CYII5SC1300AB-QWC

Manufacturer Part Number
CYII5SC1300AB-QWC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYII5SC1300AB-QWC

Lead Free Status / RoHS Status
Not Compliant
Serial 3-Wire Interface
The serial 3-wire interface (or serial-to-parallel Interface) uses a
serial input to shift the data in the register buffer. When the
complete data word is shifted into the register buffer the data
word is loaded into the internal register where it is decoded. (See
Figure
S_DATA (11:0) data bits REG_DATA (11:0). When S_EN is
asserted the parallel data is loaded into the internal registers of
Timing Diagrams
Frame Rate
The pixel rate for this sensor is high enough to support a frame
rate of >100 Hz for a window size of 640 x 480 pixels (VGA
format). Taking into account a row blanking time of 3.5 µs (as
baseline, see also
on page 17), this requires a minimum pixel rate of nearly 40 MHz.
The final bandwidth of the column amplifiers, output stage, and
others is determined by external bias resistors. With a nominal
pixel rate of 40 MHz, a full frame rate of a little more than 27
frames per second is obtained.
The frame period of the IBIS5-B-1300 sensor depends on the
shutter type.
Rolling Shutter
=> Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with:
Nr. Lines
Nr. Pixels
RBT
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal speed
(40-MHz pixel rate):
=> Frame period = (1024 * (3.5 µs + 25 ns * 1280)) = 36.4 ms
=> 27.5 fps
Global shutter
=> Frame period = Tint + Tread out
= Tint + (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with: Tint ..................................... Integration (exposure) time
Nr. Lines
Nr. Pixels
RBT
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal speed
(40 MHz pixel rate) with an integration time of 1 ms:
Document #: 38-05710 Rev. *G
19). S_DATA (15:12) address bits
Number of lines read out each frame (Y)
Number of pixels read out each line (X)
Row blanking time = 3.5 µs (typical)
Number of lines read out each frame (Y)
Number of pixels read out each line (X)
Row blanking time = 3.5 µs (typical)
Internal clock granularities (bits 4, 5, 6 and 7).
REG_ADDR (3:0);
the IBIS5-B-1300. The maximum tested frequency of S_DATA is
2.5 MHz.)
Serial 2-Wire Interface
The serial 2-wire interface is not operational in the IBIS5-B-1300
image sensor. Please use the 3-wire SPI interface for loading the
sensor registers.
37.4 ms
Region-Of-Interest (ROI) Read Out
Windowing is easily achieved by uploading the starting point of
the X- and Y-shift registers in the sensor registers using the
various interfaces. This downloaded starting point initiates the
shift register in the X- and Y-direction triggered by the Y_START
(initiates the Y-shift register) and the Y_CLK (initiates the X-shift
register) pulse. The minimum step size for the x-address is two
(only even start addresses are chosen) and one for the
Y-address (every line is addressable). The frame rate increases
almost linearly when fewer pixels are read out.
overview of the achievable frame rates (in rolling shutter mode)
with various ROI dimensions.
Table 20. Frame Rate vs. Resolution
Timing Requirements
There are six control signals that operate the image sensor:
The external system generates these control signals with
following time constraints to SYS_CLOCK (rising edge = active
edge):
T
T
=> Frame period = 1 ms + (1024 * (3.5 µs + 25 ns * 1280)) =
• SS_START
• SS_STOP
• Y_CLOCK
• Y_START
• X_LOAD
• SYS_CLOCK
SETUP
HOLD
1280 x 1024
Resolution
640 x 480
100 x 100
Image
(X*Y)
> 7.5 ns
>7.5 ns
=> 26.8 fps
Frame Rate
[frames/s]
1657
100
27
Readout Time
CYII5SM1300AB
Frame
[ms]
0.6
36
10
Table 20
Full resolution.
ROI read out.
ROI read out.
Page 20 of 34
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