CYIS1SM1000AA-HHC Cypress Semiconductor Corp, CYIS1SM1000AA-HHC Datasheet - Page 7

• Manufacturer Part Number: CYIS1SM1000AA-HHC
• Description: Image Sensor Monochrome CMOS 1024x1024Pixels 84-Pin JLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOSr

Specifications of CYIS1SM1000AA-HHC

• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1024x1024Pixels
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 60C
• Package Type: JLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package: 84JLCC
• Image Size: 1024x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 60 °C
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Not Compliant

Architecture
Floor Plan
The image sensor contains five sections: the pixel array, the X-
and Y- addressing logic, the column amplifiers, the output
amplifier and the ADC.
sensor, including an indication of the main control signals. The
following paragraphs explain the function and operation of the
different imager parts in detail.
Pixel Array
The pixel array contains 1024 by 1024 active pixels at 15 μm
pitch. Each pixel contains one photo diode and three transistors
(Figure
The photo diode is always in reverse bias. At the beginning of
the integration cycle, a pulse is applied to the reset line (gate of
T1) bringing the cathode of D1 to the reset voltage level. During
the integration period, photon-generated electrons accumulate
on the diode capacitance reducing the voltage on the gate of T2.
The real illumination dependent signal is the difference between
the reset level and the output level after integration. This
difference is created in the column amplifiers. T2 acts as a
source follower and T3 allows connection of the pixel signal
(reset level and output level) to the vertical output bus.
Document Number: 38-05714 Rev. *D
Reset_DS
A0....A9
Clk_X
Ld_X
Reset
Ld_Y
R
Vref
S
4).
10
10
Figure 3
Y Address
and Logic
Decoder
shows an outline diagram of the
Rst
Rd
1024
1024
10
1024
1024
1024
Rst
Rd
Figure 3. STAR1000 Floor Plan
Col
1024
X Address Decoder
Column Amplifiers
1024 x 1024 pixels
X Register
Pixel Array
1024
The reset lines and the read lines of the pixels in a row are
connected together to the Y- decoder logic; the outputs of the
pixels in a column are connected together to a column amplifier.
Figure 4. Architecture of the 3T Pixel
Reset
Sig
Rst
T1
Progr. Gain
Amplifier
T2
10-bit ADC
Read
T3
Buffer
10
STAR1000
Page 7 of 20
Clk_ADC
D0...D9
Ain
Aout
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