MCM20027IBMN Freescale, MCM20027IBMN Datasheet
MCM20027IBMN
Specifications of MCM20027IBMN
Related parts for MCM20027IBMN
MCM20027IBMN Summary of contents
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... This document contains information on a new product.Specifications and information herein are subject to change with- out notice. MOTOROLA, INC. 2002 Order this document by MCM20027/D Part Number MCM20027IBBL 2 C interface MCM20027IBMN For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS MCM20027 1.3 Megapixel Description ...
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... MOTOROLA o C Digital Control Sensor Interface I2C Serial Interface 10 Bit Global Global Gain Offset ADC For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS MCLK INIT STROBE SYNC SCLK SDATA Post ADC ADC(9:0) HCLK Control Signal VCLK Encoding SOF Revision 8 Oct 2002 : ...
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... Color Sequencer Global Global PGA PGA Dova 0.88x - 2.84x 0.696x - 7.48x P ost ADC P rocessing Analog Circuits Digital Logic for more information For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS 4Da rk +4Is olati on 104 8 1 INIT Serial SDATA Interface 29 SCLK 43 MCLK 2 ...
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... Exposure Global Gain PGA............................................................ Gain Modes..................................................................................... 7.4.3 7.5 Global Digital Offset Voltage Adjust (DOVA)................................ 7.6 Analog to Digital Converter (ADC)................................................ 8.0 MCM20027 Sensor External Controls........................................... 8.1 Initialization .................................................................................... 8.2 Standby Mode............................................................................... MOTOROLA Table Of Contents For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS ...
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... Register Reference Map ................................................................ 13.0 Detailed Register Block Assignments.......................................... 14.0 Electrical Characteristics .............................................................. 15.0 MCM20027 Pin Definitions............................................................. 16.0 MCM20027 Packaging Information................................................ 17.0 MCM20027 Typical electrical connection..................................... Revision 8 Oct 2002: MCM20027 Table Of Contents 2 C Bus Protocol ........................................................ For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS ...
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... Roadrunner Application May 4 2001 Note Optic Application note Feb 7 2001 Semiconductor Technical Applications - July 19 2002 MCM20027 External Resistor Table 1. Reference Documentation For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Release Contact/Location of Info Date http://www.motorola.com/sps http://www.motorola.com/sps Revision 8 Oct 2002 : MCM20027 6 ...
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... Global “Pro- 1. ImageMOS is a Motorola trademark and “Global 2. Patents held jointly by Motorola and Kodak 19) can 3. Kodak Patent pending For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS 2 C com- “Electri- 53) with no additional bias- “MCM20027 Packaging Information” (1) sensor comprises of 3 ...
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... Transfer Gate 2 and the Reset Gate open (On). Af- ter 1 Row Period [T (Off). This action causes Photodiode 2 to start charging. When the integration (charging) of Photdiode 1 has neared completion, @ T=3, the Reset Gate closes (Off). For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS ROW SELECT GATE T ...
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... The fill factor of the pix- els without microlenses is 32%. With Microlens the fill factor improves to approximately 45% to 50%. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS ...
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... Signal SOF VCLK End Of Frame Table 2. Video Encoded Signal Definitions Cap- 48. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS “Integration Time in CFRS mode:” on Figure 6, on page 11 and 12. allows the user to select how the output Pixel Data Stream Signal Control ...
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... Row Time = 1338 MCLKs WOI = 1280 Columns x 1024 Rows starting at row 16, column 8 Figure 6. CFRS Default Frame Waveform Row Time = vcw + 39 d row 16 Valid Pixel Data For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS 14). This process continues until all row 17 MOTOROLA 11 ...
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... Control Register, (Table 32), on page An example of Bayer space sub-sampling is shown in Figure 10 1295 Figure 10. Bayer Space Sub-sampling Example For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Standard Frame Timing (Figure 18) “Active Window of 12). Subsampling enables the Sub- 49 Sub-sample Control Register = R ...
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... In Continuous Frame Rolling Shutter (CFRS) capture mode, the Integration time upper limit is bounded by the Frame time (see Frame Time/Rate:” on page row and Table 45 on For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS = (cint + int d row is the number of virtual row times desired ...
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... Frame Time in SFRS mode = T frame Results Capture Mode CFRS SFRS NOTE!! CFRS Integration time = 34.5ms because: (see “Integration Time in CFRS mode:” on page For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS and cint are typically varied frame (1290 + 19) / 13.5e6 = 98.44 s =(350+1)*98.44 s =34 ...
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... The user can disable this function via the Register; Table 56 Configuration Register, Table 21, on page 41 which will allow the ASP chain to drift in offset Per-Column Digital Offset Voltage Adjust (DOVA), and controls the number of rows to clamp on. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Cap LRCA 0.1 f CLRCA ...
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... RAW or LIN or LIN2 (Table 27), on page gain via the ble 25), on page 2 C interface For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS (Table 10 Figure 4, the Color Gain Register the Color 6 ...
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... RAW 0-32 33-63 LINEAR 0-47 Red Pixel Data Green-Blue Pixel Data For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS White Balance Gain modes and Gain and Exposure Gain modes and Gain for more info. Gain Gain Formula Range 0.6956 + (0.02174* cg1 ) 0 ...
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... RAW 0-32 33-63 LINEAR 0-47 LINEAR 2 0-63 Exposure PGA Gain Exposure PGA Gain Register A Register B For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Gain Gain Formula Range 0.6956 + (0.02174* gg1 ) 0.69-1.39 d 1.391+ (0.0434* (gg1 -32) 1.39-2.74 d 0.6956 +(0.0434 x gg1 ) 0 ...
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... The default input range for the ADC is 1.9V for VREFP and 0.6V for VREFM hence allowing a 10 bit digitization of a 1.3V peak to peak signal. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS input (2.5 pp ...
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... No image frame Start of new No Yes image frame Continue No Yes current frame For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS 41. Writing a Comparison of the 3 Reset and Power 2 C register program- 42. Writing a “0” re- Comment Enable By -Forces all digital outputs to tristate -Reset all I2C values to default ...
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... Note - The External Bias resistor Input pin (EXTRESP - pin #20) should be connected to the ETRESRTN (pin#19) in the manner described in the di- agram below. EXTRESP (pin #20) EXTRESRTN (pin #19) 0.1 F 0.1 F For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS to bit res of the Power Configuration Regis- Resistor MOTOROLA 21 ...
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... HCLK signal refer to Figure 15, on page Figure 15, on Figure 7, on page 11 24. t hsync dsof t dfhclk For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Figure 20, on page 67). VCLK Delay Register, and SOF & VCLK Signal Length 57. For timing di- toFig- 22, Figure 6, on page ...
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... Falling edge of MCLK to falling edge of HCLK delay time dfhclk t MCLK to ADC[9:0] delay time dadc t MCLK to STROBE delay time strobe Revision 8 Oct 2002 : MCM20027 Figure 15) Characteristic For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Min Typ Max Unit 1 11.5 13.5 MHz 3 ...
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... T int T int T int T int T T row row T strobe2 T strobe1 For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS “Frame Rate and In- 13). The start of the ) before the first Row begins to Read- row . A sample timing dia- row Figure 16 row row row row Revision 8 ...
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... T strobe2 = 295us Results: Signal T row T int T strobe1 T strobe2 T frame NOTE!! Refer to analysis For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS ) is the main variable used to control min +1)*T min row = (1290 + 19) / 13.5e6 = 98.44 s +1)*T min row +x where x > where x > ...
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... SDATA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS . The transmitted b Figure 17 ...
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... Slave devices may hold the SCLK low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCLK line. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Figure 18, a Repeated START signal is be- ...
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... MCM20027 transi- tions to slave-receiver • Master does not send an acknowledgment (NAK) Figure 17): • Master transmits STOP to end the read cycle , 102 , h d Figure 18): , 102 , h d 103 , h, d For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Revision 8 Oct 2002 : MCM20027 28 ...
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... Ack Bit fromMCM20027 The MCM20027 transitions from a “SLAVE-transmitter” LSB to a “SLAVE-receiver” after the register data is sent Stop Signal from MASTER Figure 18. READ Cycle using Bus For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS LSB Ack Repeated Bit Start from ...
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... MOTOROLA 6 TIMING SPECIFICATIONS (see Characteristic SCLK low period = (0.2)*VDD (.8)*VDD SDATA hold time SCLK high period SDATA setup time SERIAL INTERFACE TIMING SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Figure 19) Min Max Unit 50 400 KHz MCLK MCLK ...
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... Register Name New Values Values Table Table For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS 1 RE- Required Register Default Val- for more detailed Internal Bias Current for more information on Comment Comment 02 Holds all digital circuitry in State Reset h while the I2C programming is implemented ...
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... Blue- 0E Unused FUO Table Address Assignments For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Block Name Analog Register Interface h Sensor Interface h Column Offset coeff Address Range Assignments Ref. Shadowed Table Table 10, page 35 Yes h Table 11, page 35 Yes h Table 12, page 36 ...
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... Unused Unused Unused Address Assignments (Continued) For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Ref. Shadowed Table Table 23, page 42 h Table 24, page 43 h Table 28, page Table 26, page 45 Yes h Table 27, page Table 30, page Table 31, page 48 Yes h Table 32, page 49 Yes h Table 33, page 50 ...
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... Mod64 Column Offset registers C0 - Table 9. I MOTOROLA Default Unused Unused 00 Unused 2 C Address Assignments (Continued) For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Ref. Shadowed Table Table 47, page 56 Yes h Table 48, page Table 49, page Table 49, page Table 51, page Table 52, page 59 Yes h Table 53, page 60 ...
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... Table 10. DPGA Color 1 Gain Register DPGA Color 2 Gain Code Red cg2[5] cg2[4] cg2[3] Description Table 11. DPGA Color 2 Gain Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Color Tile Configuration 11, Table 12, and Table 13. Gain for each in- (PGA Gain Mode; Table 27).The user Default ...
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... Gain = 1.391+ (0.0434* (cg3 d d Table 12. DPGA Color 3 Gain Register DPGA Color 4 Gain Code Green of Blue-Green Row cg4[5] cg4[4] cg4[3] Description Table 13. DPGA Color 4 Gain Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) cg2[2] cg2[1] cg2[0] 001110 b ) ...
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... For the default Bayer configuration of the color filter ar- ray; Figure follows: Reg (01 (00 ): red pixel; Reg ( for (02 ):green pixel of a blue-green row. The predefined h 2.2. The user should For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) cg4[2] cg4[1] cg4[0] 001110 ) d -32 Default 05 ...
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... Description Table 15. Color Tile Row 1 Definition Register Color Tile Row 2 Definition Blue - Green Row r2c3[0] r2c2[1] Description Table 16. Color Tile Row 2 Definition Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) r1c2[0] r1c1[1] r1c1[0] Reset State ...
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... Description Table 17. Color Tile Row 3 Definition Register Color Tile Row 4 Definition Unused r4c3[0] r4c2[1] Description Table 18. Color Tile Row 4 Definition Register Table 20, value in the h For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) r3c2[0] r3c1[1] r3c1[0] Reset State ...
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... Programable Bias Generator Control register; Ta- ble 24. When this bit is disabled, it will use the power config- Power ured by the internal or external resistor (bit 3). Fig 11 depicts the For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) nrv[2] nrv[1] ...
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... Setting the sit bit allows the user to completely reset the MCM20027 to the default state via the serial control In- terface. For both reset bits, ssr and sit, the user must return those bits enable continued operation For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default 00 ...
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... Table 22. Reset Control Register is used to set bit is reset (i.e. “0”) the pixel output data is set to Tristate mode. Tristate Control FUO FUO FUO Description Table 23. Tristate Control Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) sir ssr sit Reset State ...
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... Half Current (Power) consumption [40/50] = Full Current (Power) consumption [80/100] = Half Current (Power) consumption [40/50] = Full Current (Power) consumption [80/100] = Half Current (Power) consumption [40/50] = Full Current (Power) consumption [80/100] = Half Current (Power) consumption [40/50] For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default ...
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... If Exposure PGA Global Gain gg1[5] gg1[4] gg1[3] Description = 0-32 ] ---> Gain = 0.6956 + (0.02174* gg1 33-63 ] --> Gain = 1.391+ (0.0434* (gg1 d d For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) wbp cdp fcp 0 b Default lsb (0) gg1[2] ...
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... PGA Global Gain B Register= Not used The wbm bit sets the White Balance mode. While the egm[d] bit sets the Exposure gain mode PGA Gain Mode Description Table 27. PGA Gain Mode For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) gg2[2] gg2[1] gg2[0] Reset ...
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... Description = Positive Offset = Negative Offset (64 steps @ 2.6mV /Step) d Table 28. Column DOVA DC Register are used basis.i.e. Register 80 Column 0 , Register 81 Column 1, Register BF Column 63, Register 80 to Column 0..etc.. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) wbm egm[1] egm[0] xxxx 0 ...
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... The MCM20027 is in CFRS in default. The user may use this bit to capture data in the CFRS mode and/or SFRS while using the SYNC pin. The SYNC pin triggers 31, defines a single frame of data to be output from the device in the For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default 00 2 ...
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... The pixels will be read in monochrome mode in default. The row sub sampling rate is defined by rf[1:0] while the column sub sampling rate is defined by cf[1:0]. The pix- el array is fully sampled in default. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default 2A h ...
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... STROBE Pin high until it is reset back to 0. When this bit is set high - the sae and saw bit set- tings become negligible. NOTE! Please refer to Signal timing diagram. For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default 10 h ...
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... WOI Column Depth; wcd[10:0], has d a range of 0 (Table 34 and Table The user should be careful to create a WOI that con- (Table 38 tains active pixels only. There is no logic in the sensor to d For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb ( Reset ...
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... Description Table 35. WOI Row Pointer LSB Register WOI Row Depth MSB Description Table 36. WOI Row Depth MSB Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) wrp[10] wrp[9] wrp[8] Reset State xxxxx (Table 35), ...
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... WOI Row Depth LSB wrd[5] wrd[4] wrd[3] Description + 1. d Table 37. WOI Row Depth LSB Register WOI Column Pointer MSB Description Table 38. WOI Column Pointer MSB Register For More Information On This Product, Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) wrd[10] wrd[9] wrd[8] (Table 37), 011 b Default ...
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... WOI Column Pointer LSB wcp[4] wcp[3] wcp[2] Description WOI Column Width MSB wcw[10] Description WOI Column Width LSB wcw[4] wcw[3] wcw[2] Description + to: www.freescale.com ImageMOS ImageMOS Default lsb (0) wcp[1] wcp[0] Reset State (Table 00001000 b (col. 8) Default lsb (0) wcw[9] wcw[8] Reset State xxxxx ...
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... The Virtual Frame completely defines the integration time in CFRS. Any changes to the WOI or how the WOI Inte- is sampled has no effect on integration time. Integration Time Integration Time MSB 4 3 cint[12] cint[11] Description Factory Use Only Go to: www.freescale.com ImageMOS ImageMOS 56) Default lsb (0) cint[10] cint[9] ...
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... Virtual Frame Row Depth MSB 4 3 vrd[12] vrd[11] vrd[10] Description 45) Register, forms the 14-bit Virtual Frame Row Depth Virtual Frame Row Depth LSB 4 3 vrd[4] vrd[3] vrd[2] Description Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) cint[1] cint[0] Reset State 42) Register, 11111111 b ...
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... Description (Table 47) Register, forms the 14-bit Virtual Frame Col- Virtual Frame Column Width LSB 4 3 vcw[4] vcw[3] vcw[2] Description (Table 46) Register, forms the 14-bit Virtual Frame Col to: www.freescale.com ImageMOS ImageMOS Default lsb (0) vrd[1] vrd[0] 00100111 b (1064 rows) Default 05 ...
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... Description Table 49. VCLK Delay Register SOF and VCLK Signal Length Control sofc[3] Description = 1 MCLK Wide MCLKs Wide MCLKs Wide b = Full Row Wide b Go to: www.freescale.com ImageMOS ImageMOS SOF & VCLK Register, Table used to de- Default lsb (0) sofd[2] sofd[1] sofd[0] Reset State ...
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... SOF and VCLK Signal Length Control sofc[ MCLK Wide MCLKs Wide MCLKs Wide b = Full Row Wide b allows the user to choose if the column and row addresses Greycode and Readout Control gcr Description Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) sofc[2] vckc[1] vckc[ Default lsb (0) ...
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... Timing Control Register 2 (shr Internal Timing Control 4 3 shs[4] shs[3] shs[2] Description = 64 MCLKs Wide MCLKs Wide MCLKs Wide MCLKs Wide MCLKs Wide to: www.freescale.com ImageMOS ImageMOS Default lsb (0) rrr rrc Default lsb (0) shs[1] shs[0] Reset State xx 001010b Revision 8 Oct 2002 : MCM20027 ...
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... MCLKs Wide MCLKs Wide MCLKs Wide MCLKs Wide b d HCLK Control 4 3 FUO FUO hckd[2] Description Table 54. HCLK Delay Register Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) shr[1] shr[0] Reset State xx 001010b Default lsb (0) hckd[1] hckd[0] Reset State x Revision 8 Oct 2002 : ...
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... MOTOROLA, INC. 2002 For More Information On This Product, HCLK Control 4 3 FUO FUO hckd[2] Table 54. HCLK Delay Register allows the user to select how the output pixel data stream is encoded/for- and Figure 14, on page 20) Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) hckd[1] hckd[0] 100 b Figure Revision 8 ...
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... NOTE! Since there exists ONLY 11 dark rows the addition of FRC Row Depth + FRC Row Start should not be great- er than 11, otherwise light rows would be clamped in the process. MOTOROLA, INC. 2002 For More Information On This Product vcc FUO Description allows the user to define the size of the dark rows to use as Clamping rows. Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) FUO ...
Page 63
... Defines the first Clamping row. Defines the FRC starting point. Start MOTOROLA, INC. 2002 For More Information On This Product, FRC Definition 4 3 frcd[0] frcs[3] frcs[2] Description Factory Use Only . d Table 56. FRC Definition Register Go to: www.freescale.com ImageMOS ImageMOS Default lsb (0) frcs[1] frcs[0] Reset State x 10 ...
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... Analog Circuit Analog Circuit Parameter Min. = 3.3V (Nominal) 3 and V be constrained to the range V < out SS = 3.3V 0.3V; V referenced Condition to: www.freescale.com ImageMOS ImageMOS Value Unit -0 100 mA -65 to +125 °C 300 °C Max Unit 3 °C 55 ° < out 0°C to 40°C) ...
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... DD OL Output = High Impedance out I = 0mA out in DD Condition INIT Pin Logic High 13.5 MHz Operation Typ 0. Typ 0.3 = 650 550 450 nm 8 Typ 1.8 0.2 0.4 0.9995 Go to: www.freescale.com ImageMOS ImageMOS - 100 mW SS Typ Unit 100 uW 250 mW Unit Notes ...
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... ADC. MOTOROLA, INC. 2002 For More Information On This Product, 11.5 200 ) that the device can be exposed to before blooming of the pixel will sat GENERAL Typ 70 50 Analog to Digital Converter (ADC) Min 8 Go to: www.freescale.com ImageMOS ImageMOS MHz 4 2,3 Unit Notes - 1 e rms dB Typ ...
Page 67
... A = Analog AVSS AVDD CLRCA See Section 8.4 for more information MOTOROLA, INC. 2002 For More Information On This Product, Top-View Figure 20. MCM20027 Pin Definitions Go to: www.freescale.com ImageMOS ImageMOS note: pins 1 & 46 should be pulled down when not in use SDATA SCLK DVDD DVSS VSS_PIX ...
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... STROBE I 48 SOF Table 57. MCM20027 Pin Definitions I INPUT P POWER G GROUND O OUTPUT D DIGITAL A ANALOG I/O BIDIRECTIONAL Go to: www.freescale.com ImageMOS ImageMOS Pin Description Power Type Pixel power Pixel ground Digital Ground G D Digital Power P D I2C Serial Clock I/O I2C Serial Data I/O ...
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... B 0.525 C --- D 0.016 E 0.054 F 0.075 G 0.040 BSC H 0.033 J 0.555 K 0.525 R 0.0075 (Radius) R1 0.0075 (Radius) MOTOROLA, INC. 2002 For More Information On This Product, Max(Inches) 0.572 0.545 0.09362 0.024 0.068 0.095 0.047 0.572 0.545 Go to: www.freescale.com ImageMOS ImageMOS Revision 8 Oct 2002 : MCM20027 69 ...
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... X-Offset: +52µm (~2mil) X-axis Offset +182µm (~7 mil) Y-Offset: +400µm (~16mil) Die Placement positional tolerance 200um (+/- 4 mil TST_VS EXT_VINR EXT_VINS AVSS VDDA CVREFM CVREFP VAG Go to: www.freescale.com ImageMOS ImageMOS PIX_OUT1 PIX_OUT2 PIX_OUT0 MOT M SDATA INC SCLK DVDD 28 19 DVSS 27 20 ...
Page 71
... Go to: www.freescale.com ImageMOS ImageMOS D English (inches) min max 0.01969 0.02362 0.03900 0.04900 0.02776 0.02933 0.01500 0.01900 0.00050 0.00300 0.00025 0.00200 0.02660 ...
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... DVSS AVSS 27 DVSS M 20027IB GND +3. .01uf .01uf to: www.freescale.com ImageMOS ImageMOS PIXE L D ATA 0 PIXE L D ATA 1 PIXE L D ATA 2 PIXE L D ATA 3 PIXE L D ATA 4 PIXE L D ATA 5 PIXE L D ATA 6 PIXE L D ATA 7 PIXE L D ATA 8 PIXE L D ATA 9 D ATA VALID ...
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... JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Go to: www.freescale.com ImageMOS ImageMOS MFax is a trademark of Motorola, Inc. ...