DM74S280M_NL Fairchild Semiconductor, DM74S280M_NL Datasheet
DM74S280M_NL
Specifications of DM74S280M_NL
Related parts for DM74S280M_NL
DM74S280M_NL Summary of contents
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features Generates either odd or even parity for nine data lines ...
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Logic Diagram Typical Applications Three DM74S280’s can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. (See Figure 1.) FIGURE 1. 25-Line Parity/Generator Checker www.fairchildsemi.com Longer word lengths can be implemented by ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...