SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 59

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

RC1: Clock Driver Enable Control Word
RC2: Timing Control Word
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
DBA1
DBA1
1
2
inputs.
x
x
x
x
x
x
0
1
x
x
x
x
x
x
0
1
A or B output disable allows the use of the SSTE32882KA1 in reduced parts count applications such as DDR3 Mini-RDIMMs.
When output disable is asserted, all outputs on the corresponding side of the register, including the clock drivers, remain in
Hi-Z at all times. When RC0[DBA0] = 1, all A-side Q-outputs and Y1 and Y3 outputs will be disabled. When RC0[DBA1] =
1, all B-side Q-outputs and Y0 and Y2 outputs will be disabled. When RC0[DBA0] = 1 and RC0[DBA1] = 1, all A-side and
B-side Q-outputs and Yn outputs will be disabled.
Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine
which clock outputs are used by the module. The PLL remains locked on CK/CK unless the system stops the clock inputs to
the SSTE32882KA1 to enter the lowest power mode.
There is no floating once 3T timing is activated.
If MIRROR is ‘HIGH’ then Input Bus Termination (IBT) is turned off, or on all inputs except the DCSn and DODTn
DBA0
DBA0
x
x
x
x
0
1
x
x
x
x
x
x
0
1
x
x
Input
Input
DA4
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
DA4
x
x
0
1
x
x
x
x
x
x
0
1
x
x
x
x
DA3
DA3
0
1
x
x
x
x
x
x
0
1
x
x
x
x
x
x
(Control Signals QxCKE, QxCS, QxODT
Address- and command-nets pre-launch
Disable Y0/Y0 clock
Disable Y1/Y1 clock
Disable Y2/Y2 clock
Disable Y3/Y3 clock
Input Bus Termination
Frequency Band Select
Definition
1T/3T Output timing
do not apply)
Definition
(2)
59
Address and command nets pre-launch (3/4
Y0/Y0 clock disabled
Y1/Y1 clock disabled
Y2/Y2 clock disabled
Y3/Y3 clock disabled
Y0/Y0 clock enabled
Y1/Y1 clock enabled
Y2/Y2 clock enabled
Y3/Y3 clock enabled
Test Mode (Frequency Band 2)
Encoding
Operation (Frequency Band 1)
Standard (1/2 Clock)
3T timing
COMMERCIAL TEMPERATURE RANGE
Encoding
1T timing
Clock)
100 Ω
150 Ω
SSTE32882KA1
(1)
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