IDT82V3001APV IDT, Integrated Device Technology Inc, IDT82V3001APV Datasheet - Page 8

• Manufacturer Part Number: IDT82V3001APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3001APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table - 1 Pin Description (Continued)
PIN DESCRIPTION
IC0, IC1, IC2
IDT82V3001A
C1.5o
TRST
Name
C32o
C16o
F32o
F16o
TDO
TMS
RSP
TCK
C8o
C4o
C2o
C3o
C6o
TSP
F8o
F0o
TDI
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
Type
I
I
-
I
I
53, 54, 55
Number
Pin
25
24
23
20
17
16
15
14
40
39
36
33
41
42
29
32
30
28
31
Clock 32.768 MHz.
This output is a 32.768 MHz clock used for ST-BUS operation.
Clock 16.384 MHz.
This output is a 16.384 MHz clock used for ST-BUS operation.
Clock 8.192 MHz.
This output is an 8.192 MHz clock used for ST-BUS operation.
Clock 4.096 MHz.
This output is a 4.096 MHz clock used for ST-BUS operation.
Clock 2.048 MHz.
This output is a 2.048 MHz clock used for ST-BUS operation.
Clock 3.088 MHz.
This output is a 3.088 MHz clock used for T1 applications.
Clock 1.544 MHz.
This output is a 1.544 MHz clock used for T1 applications.
Clock 6.312 MHz.
This output is a 6.312 MHz clock used for DS2 applications.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 31 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state if JTAG scan is
not enabled.
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in Test-Logic-Reset state. This pin is internally pulled up to
V
Test Clock.
Provides a clock to JTAG test logic.
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V
Internal Connection.
Internal Use. These pins should be connected to V
DDD
. It is connected to the ground for normal applications.
8
SS
when in normal operation.
Description
WAN PLL WITH SINGLE REFERENCE INPUT
DDD
October 15, 2008
.
DDD
.