ICS87158AFT IDT, Integrated Device Technology Inc, ICS87158AFT Datasheet - Page 12

• Manufacturer Part Number: ICS87158AFT
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS87158AFT

• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Package Type: SSOP
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

87158AG
L
The logic input control signals are 3.3V LVCMOS compatible.
The logic control input contains ESD diodes and either pull-up
or pull-down resistor as shown in Figure 5. The data sheet pro-
vides pull-up or pull-down information for each input pin. Leav-
ing the input floating will set the control logic to default setting.
HCSL D
The HCSL is a differential constant current source driver. The
output current is set by control pins MULT_[1:0] and the value of
resistor Rref.
In the characteristic impedance of 50 Ohm environment, the
match load 50 Ohm resistors R4 and R5 are terminated at the
receiving end of the transmission line. The 33 Ohm series resis-
tor R6 and R7 should be located as close to the driver pins as
possible. For the clock traces that required very low skew should
have equal length.
Other general rules of high-speed digital design also should be
followed. Some check points are listed as follows:
OGIC
C
ONTROL
RIVER
INPUT_PU
A) Input with internal pull up resistor
T
ERMINATION
I
NPUT
RU
51K
VDD
D1
D2
F
IGURE
5. L
www.idt.com
OGIC
12
I
To set logic high, the input pin connected directly to V
logic low, the control input connect directly to ground. For con-
trol signal source from the driver that has different power sup-
ply, a series current resistor of greater than 100 Ohm is required
for random power on sequence.
-
-
-
-
-
NPUT
Avoid sharp angles on the clock trace. Sharp angle turn
causes the characteristic impedance change on the
transmission lines.
Keep the clock trace on same layer. Whenever possible,
avoid any vias on the middle clock traces. Any via on
middle the trace can affect the trace characteristic
impedance and hence degrade signal quality.
There should be sufficient space between the clock traces
that have different frequencies to avoid cross talk.
No other signal trace is routed between the clock trace
pair.
Transmission line should not be routed across the split
plane on the adjacent layer.
INPUT_DOWN
1-
C
B) Input with internal pull down resistor
ONTROLS
TO
-6, LVPECL-
÷1, ÷2, ÷4 C
RD
51K
TO
VDD
D1
D2
-HCSL/LVCMOS
LOCK
ICS87158
G
REV. C JULY 25, 2010
ENERATOR
DD
. To set