TDA9950TT/C2 NXP Semiconductors, TDA9950TT/C2 Datasheet - Page 5

• Manufacturer Part Number: TDA9950TT/C2
• Manufacturer: NXP Semiconductors

Specifications of TDA9950TT/C2

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: TSSOP
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
TDA9950_2
Product data sheet
8.2 Configuring the TDA9950
8.3 Use of the INT line
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I
The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when
connected to V
The TDA9950 is controlled via a series of registers.
Table 5.
The first byte of any I
which determines the first TDA9950 register that will be read or written in the remainder of
the I
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Registers 01h to 06h are used for configuration of the TDA9950, whilst repeated
auto-incremented reads starting at register 07h are used to transfer CEC data. Setting the
address pointer register higher than 07h is treated as setting it to 07h, as all message
data transfers must start from register 07h and continue by auto-incrementing in one
contiguous transfer. Transfers via the data registers are formatted using the data register
protocol described in
As the TDA9950 is an I
the host that data is available for reading. This is the INT output line, which should be
monitored by the host. An additional TDA9950 input, on pin INT_POL, allows
configuration of the polarity of operation of the INT line. When the INT line is active, it will
match the state of the input on pin INT_POL.
The state of the INT line is always reflected in the TDA9950 Status Register, so it is
possible to regularly poll this register instead of monitoring the INT line. However, this
method is less efficient and not recommended. The INT indication in the TDA9950 Status
Register is not affected by the setting of the INT polarity input on pin INT_POL.
Register
APR
CSR
CER
CVR
CCR
ACKH
ACKL
CCONR
CDR
2
C-bus transfer. If a read is carried out without a prior write to the address pointer
2
C-bus.
I
2
C-bus register configuration
DD
Description
Address Pointer Register
TDA9950 Status Register
TDA9950 Error Register
TDA9950 Version Register
TDA9950 Control Register
CEC Address ACK High register
CEC Address ACK Low register
CEC Configuration Register
CEC Data Registers
, logic 0 when connected to GND).
2
Section
Rev. 02 — 22 October 2009
C-bus write frame configures the address pointer register APR,
2
C-bus slave device, it provides an additional I/O line to signal to
8.5.
Address
00h
00h
01h
02h
03h
04h
05h
06h
07h - 19h
CEC/I
TDA9950
© NXP B.V. 2009. All rights reserved.
2
C-bus translator
Read/Write
W
R
R
R
R/W
R/W
R/W
R/W
R/W
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