N74F524N NXP Semiconductors, N74F524N Datasheet - Page 4

• Manufacturer Part Number: N74F524N
• Manufacturer: NXP Semiconductors
• Type: Magnitude Comparatorr

Specifications of N74F524N

• Logic Family: F
• Technology: Bipolar
• Low Level Output Current: 24mA
• Output Function: A<B, A=B, A>B
• Package Type: PDIP
• Mounting: Through Hole
• Pin Count: 20
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Number Of Bits: 8
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
CS/O output of the most significant device will be forced Low,
disabling the subsequent devices but enabling its own status
outputs. The corrected status condition is thus indicated. The same
applies if the register byte is less than the data byte, only in this
case the EQ and GT outputs go Low, whereas the LT output floats
High.
If an equality condition is detected in the most significant device, its
C/SO output is forced High. This enables the next less significant
APPLICATION
FUNCTION TABLE
(1) = High if I/On=Dn, otherwise Low
2 = Must meet setup and hold time requirements
H = High voltage level
L = Low voltage level
X = Don’t care
1990 Aug 07
WR
SE
RD
8-bit register comparator (open collector + 3-State)
H
H
H
H
H
H
H
L
L
L
L
L
L
H = TWO’s COMPLEMENT
L = MAGNITUDE
C/SI
H
X
H
H
H
H
H
L
L
L
L
L
L
H or L
H or L
H or L
H or L
H or L
H or L
H
S0
H
H
H
L
L
L
L
2
2
2
2
2
2
C/SI
H or L
H or L
H or L
H or L
H or L
H or L
M
S1
H
H
H
H
L
L
L
INPUTS
S0
2
2
2
2
2
2
GT
GREATER THAN
S1
Figure 1. Cascading 74F524s for Comparing Longer Words
MSB
EQ
EQUAL TO
I/O
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
Data comparison
C/SO
LT
8
LESS THAN
SE
X
X
X
X
X
X
X
C/SI
M
L
S0
4
GT
device and disables its own status outputs. In this way, the status
output proximity is handed down to the next less significant device
which now effectively becomes the most significant byte. The worst
case propagation delay for a compare operation involving ‘n’
cascaded 74F524s will be when an equality condition is detected in
all but the least significant byte. In this case, the status priority has
to ripple all the way down the chain before the correct status output
is established. Typically, this will take 35+6(n–2) ns.
EQ
S1
H
H
H
H
H
H
H
H
H
L
L
L
L
EQ
I/O
GT
OUTPUTS
LT
C/SO
8
H
H
H
H
H
H
H
H
H
H
H
L
L
SE
LT
H
H
H
H
H
H
H
H
H
H
H
L
L
C/SO
C/SI
Q0
(1)
(1)
(1)
H
L
L
L
L
L
L
L
L
L
M
S0
GT
S1
OPERATING MODE
OPERATING MODE
EQ
LSB
(GT=CT=off)
(GT=CT=off)
(GT=CT=on)
(GT=CT=on)
I/O
Compare
Compare
Read
Read
Load
Load
C/SO
Hold
Hold
LT
8
Shift
Product specification
SE
74F524
SF01012
V
CC
L