SSTUB32866BHLF IDT, Integrated Device Technology Inc, SSTUB32866BHLF Datasheet - Page 16

• Manufacturer Part Number: SSTUB32866BHLF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32866BHLF

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

2. Device standard (cont'd)
1165A—3/21/07
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
‡
§
†
(not used)
PAR_IN †‡
D1•D14 †
Q1•Q14
QERR# §
After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
PAR_IN is driven from PPO of the first SSTU32866 device.
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
RST#
DCS#
CSR#
CK
CK#
PPO
t act
pair; C0=1, C1=1; RST# switches from L to H
t pdm , t pdmss
n
t su
H, L, or X
CK to Q
Data to QERR# Latency
CK to QERR#
16
n + 1
t PHL
t h
n + 2
CK to PPO
t su
Advance Information
t pd
H or L
CK to QERR#
ICSSSTUB32866B
n + 3
t PHL , t PLH
t h
n + 4
ACT