SR1530HCLR Intel (CPU), SR1530HCLR Datasheet - Page 17

• Manufacturer Part Number: SR1530HCLR
• Manufacturer: Intel (CPU)

Specifications of SR1530HCLR

• Lead Free Status / RoHS Status: Not Compliant

Intel
3.1
The memory controller hub (MCH) is a single 1432 pin FCBGA package that includes these
core platform functions:
3.1.1
The MCH is configured for symmetric multi-processing across two independent front side bus
interfaces that connect to the processors. Each front side bus on the MCH uses a 64-bit wide
1066- or 1333-MHz data bus. The 1333-MHz data bus can transfer data at up to 10.66 GB/s.
The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory.
The MCH is the priority agent for both front side bus interfaces, and is optimized for one
processor on each bus.
3.1.2
The server board supports one or two Dual-Core Intel
voltage Quad-Core Intel
and 1333 MHz, and core frequencies starting at 1.6 GHz. Previous generations of the Intel
Xeon
For a complete list of supported processors, see the following link:
http://support.intel.com/support/motherboards/server/S5000VCL
Note: Only Dual-Core Intel
Xeon
supported.
Revision 2.2
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Server Board S5000VCL TPS
processor are not supported.
processor 5300 series, that support system bus speeds of 1066 MHz, and 1333 MHz are
Intel
System bus interface for the processor sub-system
Memory controller
PCI Express* ports including the enterprise south bridge interface (ESI)
FBD thermal management
SMBUS interface
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System Bus Interface
Processor Support
5000V Memory Controller Hub (MCH)
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Xeon
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Xeon
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processor 5300 series, with system bus speeds of 1066 MHz,
Intel order number: D64569-006
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processors 5100 series or low-voltage Quad-Core Intel
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Xeon
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processors 5100 series or low
Functional Architecture
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